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Covers MC9S12XS Family MC9S12XS256, MC9S12XS128, MC9S12XS64.) /Keywords ("mc9s12xs256, mc9s12xs, mc9s12xs256, mc9s12xs128, mc9s12xs64, s12xs family, s12xe family, can") /Producer (Normalizer 6.0 fmnorm) /CreationDate (D:20120917075006-05'00') /PXCViewerInfo (PDF-XChange Viewer;2.5.197.0;Jul 8 2011;20:50:13;D:20121005175957-05'00') >> endobj 2 0 obj << /Dests 10 0 R >> endobj 3 0 obj << /Kids [11 0 R 12 0 R 13 0 R 14 0 R 15 0 R 16 0 R 17 0 R 18 0 R] /Type /Pages /Count 738 /MediaBox [0 0 612 792] >> endobj 4 0 obj << /F 19 0 R /I << /Title (A) >> >> endobj 5 0 obj << /Type /Metadata /Length 3970 /Subtype /XML >> stream 2012-09-17T07:50:06-05:00 2012-10-05T17:59:57-05:00 FrameMaker 7.1 Normalizer 6.0 fmnorm mc9s12xs256, mc9s12xs, mc9s12xs256, mc9s12xs128, mc9s12xs64, s12xs family, s12xe family, can application/pdf MC9S12XS256 - Referece Manual Freescale Semiconductor Inc. The new S12XS family of 16-bit micro controllers is a compatible, reduced version of the S12XE family. Targeted at generic automotive applications and CAN nodes, some typical examples of these applications are: Body Controllers, Occupant Detection, Door Modules, RKE Receivers, Smart Actuators, Lighting Modules and Smart Junction Boxes amongst many others. Covers MC9S12XS Family MC9S12XS256, MC9S12XS128, MC9S12XS64. mc9s12xs256, mc9s12xs, mc9s12xs256, mc9s12xs128, mc9s12xs64, s12xs family, s12xe family, can endstream endobj 6 0 obj << /Last 20 0 R /Count 26 /First 21 0 R >> endobj 7 0 obj << /Type /metadataa /Length 3642 /Subtype /XML >> stream Normalizer 6.0 fmnorm 2012-09-19T16:31+05:30 FrameMaker 7.1 2012-09-17T12:50:06Z 2012-09-19T16:31+05:30 application/pdf MC9S12XS256 Reference Manual Freescale Inc. uuid:3da33d17-6df1-4732-96ca-34b607d38e1b uuid:5d1ae98a-3192-46e2-85a0-48d799e3f865 endstream endobj 8 0 obj << /Nums [0 22 0 R] >> endobj 10 0 obj << /Kids [23 0 R 24 0 R 25 0 R 26 0 R 27 0 R 28 0 R 29 0 R 30 0 R 31 0 R 32 0 R 33 0 R 34 0 R 35 0 R 36 0 R 37 0 R 38 0 R 39 0 R 40 0 R 41 0 R 42 0 R 43 0 R 44 0 R 45 0 R 46 0 R 47 0 R 48 0 R 49 0 R 50 0 R 51 0 R 52 0 R 53 0 R 54 0 R 55 0 R 56 0 R 57 0 R 58 0 R 59 0 R 60 0 R 61 0 R 62 0 R 63 0 R 64 0 R 65 0 R 66 0 R 67 0 R 68 0 R 69 0 R 70 0 R 71 0 R 72 0 R 73 0 R 74 0 R 75 0 R 76 0 R 77 0 R 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(I9.1.530353) 2367 0 R (I9.1.530366) 2368 0 R (I9.1.530379) 2369 0 R (I9.1.530392) 2370 0 R (I9.1.530405) 2371 0 R (I9.1.530418) 2372 0 R (I9.1.530431) 2373 0 R (I9.1.530444) 2374 0 R (I9.1.530457) 2375 0 R (I9.1.530470) 2376 0 R (I9.1.530483) 2377 0 R (I9.1.530496) 2378 0 R (I9.1.530509) 2379 0 R (I9.1.530522) 2380 0 R] /Limits [(I9.1.529658) (I9.1.530522)] >> endobj 58 0 obj << /Names [(I9.1.530535) 2381 0 R (I9.1.530548) 2382 0 R (I9.1.530561) 2383 0 R (I9.1.530574) 2384 0 R (I9.1.530587) 2385 0 R (I9.1.530600) 2386 0 R (I9.1.530613) 2387 0 R (I9.1.530626) 2388 0 R (I9.1.530639) 2389 0 R (I9.1.530652) 2390 0 R (I9.1.530665) 2391 0 R (I9.1.530678) 2392 0 R (I9.1.530691) 2393 0 R (I9.1.530704) 2394 0 R (I9.1.530717) 2395 0 R (I9.1.530730) 2396 0 R (I9.1.530743) 2397 0 R (I9.1.530756) 2398 0 R (I9.1.530769) 2399 0 R (I9.1.530782) 2400 0 R (I9.1.530795) 2401 0 R (I9.1.531148) 2402 0 R (I9.1.531166) 2403 0 R (I9.1.531179) 2404 0 R (I9.1.531192) 2405 0 R (I9.1.531205) 2406 0 R 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(I9.1.532275) 2447 0 R (I9.1.532288) 2448 0 R (I9.1.532464) 2449 0 R (I9.1.532497) 2450 0 R (I9.1.532510) 2451 0 R (I9.1.532528) 2452 0 R (I9.1.532546) 2453 0 R (I9.1.532624) 2454 0 R (I9.1.532683) 2455 0 R (I9.1.532706) 2456 0 R (I9.1.532720) 2457 0 R (I9.1.532773) 2458 0 R (I9.1.532798) 2459 0 R (I9.1.532824) 2460 0 R (I9.1.532847) 2461 0 R (I9.1.532876) 2462 0 R (I9.1.532915) 2463 0 R (I9.1.532933) 2464 0 R (I9.1.532951) 2465 0 R (I9.1.532964) 2466 0 R (I9.1.532982) 2467 0 R (I9.1.532995) 2468 0 R (I9.1.533008) 2469 0 R (I9.1.533021) 2470 0 R (I9.1.533039) 2471 0 R (I9.1.533052) 2472 0 R (I9.1.533065) 2473 0 R (I9.1.533078) 2474 0 R (I9.1.533099) 2475 0 R (I9.1.533112) 2476 0 R (I9.1.533130) 2477 0 R (I9.1.533143) 2478 0 R (I9.1.533156) 2479 0 R (I9.1.533174) 2480 0 R (I9.1.533192) 2481 0 R (L1) 2482 0 R (L10) 2483 0 R (L11) 2484 0 R (L12) 2485 0 R (L13) 2486 0 R (L14) 2487 0 R (L15) 2488 0 R (L16) 2489 0 R (L17) 2490 0 R (L18) 2491 0 R (L19) 2492 0 R (L2) 2493 0 R (L20) 2494 0 R (L21) 2495 0 R (L22) 2496 0 R (L23) 2497 0 R (L24) 2498 0 R (L25) 2499 0 R (L3) 2500 0 R (L4) 2501 0 R (L5) 2502 0 R (L6) 2503 0 R (L7) 2504 0 R (L8) 2505 0 R (L9) 2506 0 R (M10.9.17663.tabletitle.Table.11..Security.Bits) 2507 0 R (M10.9.29861.TableFootnote.1.Availability.of.Flash.arrays.in.the.memory.map.depends.on.ROMCTLEROMCTL.) 2508 0 R] /Limits [(I9.1.532244) (M10.9.29861.TableFootnote.1.Availability.of.Flash.arrays.in.the.memory.map.depends.on.ROMCTLEROMCTL.)] >> endobj 60 0 obj << /Names [(M10.9.35018.TBTitle.Table12.Feature.Availability.in.Unsecure.and.Secure.Modes.on.S12XD) 2509 0 R (M10.9.42324.tabletitle.Table.21.Backdoor.Key.Access.Enable.bits) 2510 0 R (M10.9.52665.ChpTitle.Chapter3.Block.Title.Block.Guide) 2511 0 R (M10.9.54915.tabletitle.Table.11.Features.Limited.in.Secure.Mode) 2512 0 R (M10.9.69500.TableFootnote.4.Restricted.NVM.command.set.only.Please.refer.to.the.NVM.wrapper.block.gu) 2513 0 R (M10.9.75756.TBTitle.Table12.Backdoor.Key.Access.Enable.Bits) 2514 0 R (M10.9.83449.TableFootnote.3.BDM.hardware.commands.restricted.to.peripheral.registers.only) 2515 0 R (M10.9.84924.sectionxxx.221.Unsecuring.the.MCU.using.the.Backdoor.Key.Access) 2516 0 R (M10.9.96994.TableFootnote.2.Restricted.NVM.command.set.only.Please.refer.to.the.FTXEETX.block.guides) 2517 0 R (M11.9.17842.tabletitle.Table.41.Examples.of.PLL.divider.settings) 2518 0 R (M11.9.19010.sectionxxx.521.Clock.Monitor.Reset) 2519 0 R (M11.9.21730.figuretitle.Figure.53.RESET.pin.held.low.externally) 2520 0 R (M11.9.24907.figuretitle.Figure.52.RESET.pin.tied.to.VDD.by.a.pullup.resistor) 2521 0 R (M11.9.25743.FigTitle.Figure12.CRG.Register.Summary) 2522 0 R (M11.9.27848.figuretitle.Figure.44.Sequence.for.Clock.Quality.Check) 2523 0 R (M11.9.27992.tabletitle.Table.41.MCU.configuration.during.Wait.Mode) 2524 0 R (M11.9.29344.tabletitle.Table.14.RTI.Frequency.Divide.Rates) 2525 0 R (M11.9.29565.figuretitle.Figure.42.Clock.Generator) 2526 0 R (M11.9.32888.tabletitle.Table.32.VCO.Clock.Frequency.Selection) 2527 0 R (M11.9.35181.sectionxxx.432.Self.Clock.Mode) 2528 0 R (M11.9.35993.tabletitle.Table.52) 2529 0 R (M11.9.36235.Heading4.11411.Phase.Locked.Loop.with.Internal.Filter.IPLL) 2530 0 R (M11.9.39278.figuretitle.Figure.112.Breakpoint.Register.Summary) 2531 0 R (M11.9.41823.TBTitle.Table17.FM.Amplitude.selection) 2532 0 R (M11.9.44103.figuretitle.Figure.51.RESET.Timing) 2533 0 R (M11.9.45109.figuretitle.Figure.411.Fast.Wakeup.from.Full.Stop.mode.Application.Example.2) 2534 0 R (M11.9.52665.ChpTitle.Chapter3.Block.Title.Block.Guide) 2535 0 R (M11.9.55314.sectionxxx.522.Computer.Operating.Properly.Watchdog.COP.Reset) 2536 0 R (M11.9.61607.Heading4.1433.Stop.Mode) 2537 0 R (M11.9.66562.tabletitle.Table.51.Reset.Summary) 2538 0 R (M11.9.67371.figuretitle.Figure.41.IPLL.Functional.Diagram) 2539 0 R (M11.9.69395.tabletitle.Table.32.RTI.Frequency.Divide.Rates.for.DEC0) 2540 0 R (M11.9.69410.tabletitle.Table.33.COP.Watchdog.Rates) 2541 0 R (M11.9.77228.Heading4.1415.Computer.Operating.Properly.Watchdog.COP) 2542 0 R (M11.9.77935.sectionx.Section.3.Memory.Map.and.Registers) 2543 0 R (M11.9.79619.Heading4.1324.S12XECRG.Flags.Register.CRGFLG) 2544 0 R (M11.9.81346.Heading3.151.Description.of.Reset.Operation) 2545 0 R (M11.9.85929.sectionxxx.425.Clock.Quality.Checker) 2546 0 R (M11.9.86412.figuretitle.Figure.11.Block.diagram.of.CRG) 2547 0 R (M11.9.87281.tabletitle.Table.61.CRG.Interrupt.Vectors) 2548 0 R (M11.9.90627.figuretitle.Figure.410.Fast.Wakeup.from.Full.Stop.mode.Application.Example.1) 2549 0 R (M11.9.92187.figuretitle.Figure.44.Check.window.definition) 2550 0 R (M11.9.99708.tabletitle.Table.33) 2551 0 R (M12.9.13729.sectionx.Section.3.Memory.Map.and.Registers) 2552 0 R (M12.9.14628.sectionx.Section.4.Functional.Description) 2553 0 R (M12.9.35611.figuretitle.Figure.11.OSCLCP.Block.Diagram) 2554 0 R (M12.9.52665.ChpTitle.Chapter3.Block.Title.Block.Guide) 2555 0 R (M12.9.70126.sectionx.Section.1.Introduction) 2556 0 R (M13.9.13729.sectionx.Section.3.Memory.Map.and.Registers) 2557 0 R (M13.9.14207.FigTitle.Figure12.ADC12B16C.Register.Summary.Sheet.1.of.3) 2558 0 R (M13.9.14221.tabletitle.Table.12) 2559 0 R (M13.9.14628.sectionx.Section.4.Functional.Description) 2560 0 R (M13.9.18346.tabletitle.Table.38.Left.Justified.Signed.and.Unsigned.ATD.Output.Codes) 2561 0 R (M13.9.24927.sectionxxx.3311.ATD.Conversion.Result.Registers.ATDDRx) 2562 0 R (M13.9.26906.figuretitle.Figure.11.ATD.Module.Block.Diagram) 2563 0 R (M13.9.36219.tabletitle.Table.32) 2564 0 R (M13.9.39054.sectionxxx.337.ATD.Status.Register.0.ATDSTAT0) 2565 0 R (M13.9.39278.figuretitle.Figure.112.Breakpoint.Register.Summary) 2566 0 R (M13.9.42773.Heading5.132121.Left.Justified.Result.Data) 2567 0 R (M13.9.51246.tabletitle.Table.33.External.Trigger.Channel.Select.Coding) 2568 0 R (M13.9.52665.ChpTitle.Chapter3.Block.Title.Block.Guide) 2569 0 R (M13.9.54120.tabletitle.Table.37) 2570 0 R (M13.9.58537.tabletitle.Table.33.Conversion.Sequence.Length.Coding) 2571 0 R (M13.9.59763.TBTitle.Table121) 2572 0 R] /Limits [(M10.9.35018.TBTitle.Table12.Feature.Availability.in.Unsecure.and.Secure.Modes.on.S12XD) (M13.9.59763.TBTitle.Table121)] >> endobj 61 0 obj << /Names [(M13.9.65443.tabletitle.Table.35.Sample.Time.Select) 2573 0 R (M13.9.78517.Header2.58.General.Purpose.Digital.Input.Port.Operation) 2574 0 R (M13.9.84500.tablenote.1.Only.if.ETRIG30.input.option.is.available.see.device.specification.else.ETRI) 2575 0 R (M13.9.85635.TBTitle.Table11.ATDCTL0.Field.Descriptions) 2576 0 R (M13.9.87281.tabletitle.Table.61.CRG.Interrupt.Vectors) 2577 0 R (M13.9.91564.tabletitle.Table.34.ATD.Behavior.in.Freeze.Mode.breakpoint) 2578 0 R (M13.9.92090.Heading5.132122.Right.Justified.Result.Data.DJM1) 2579 0 R (M13.9.92536.tabletitle.Table.32.Conversion.Sequence.Length.Coding) 2580 0 R (M13.9.94604.tabletitle.Table.39.Analog.Input.Channel.Select.Coding) 2581 0 R (M13.9.94911.Heading3.132.Register.Descriptions) 2582 0 R (M14.9.10258.sectionxxxx.1714.MSCAN.Bus.Timing.Register.1.CANBTR1) 2583 0 R (M14.9.11053.figuretitlewide.Figure.18.MSCAN.Clocking.Scheme) 2584 0 R (M14.9.11692.tabletitle.Table.44.Interrupt.Vectors) 2585 0 R (M14.9.11979.figuretitlewide.Figure.17.8bit.Maskable.Identifier.Acceptance.Filters) 2586 0 R (M14.9.13671.sectionxxx.1124.MSCAN.Sleep.Mode) 2587 0 R (M14.9.13729.sectionx.Section.3.Memory.Map.and.Registers) 2588 0 R (M14.9.14593.sectionxxxx.17114.MSCAN.Identifier.Mask.Registers.CANIDMR07) 2589 0 R (M14.9.14628.sectionx.Section.4.Functional.Description) 2590 0 R (M14.9.14786.sectionxxx.1104.ListenOnly.Mode) 2591 0 R (M14.9.15552.list1.1.Bosch.CAN.20AB.protocol.specification.dated.September.1991) 2592 0 R (M14.9.15734.figuretitlewide.Figure.110.CAN.Standard.Compliant.Bit.Time.Segment.Settings) 2593 0 R (M14.9.15835.sectionxxxx.1718.MSCAN.Transmitter.Control.Register.CANTCR) 2594 0 R (M14.9.15851.sectionxxxx.1717.MSCAN.Transmitter.Flag.Register.CANTFLG) 2595 0 R (M14.9.16851.figuretitle.Figure.12.User.Model.for.Message.Buffer.Organization) 2596 0 R (M14.9.17054.figuretitle.Figure54.Sleep.Request..Acknowledge.Cycle) 2597 0 R (M14.9.17577.sectionxxx.1116.MSCAN.Power.Down.Mode) 2598 0 R (M14.9.18292.sectionxxx.621.Transmit.Interrupt) 2599 0 R (M14.9.18570.figuretitlewide.Figure.19.Segments.within.the.Bit.Time) 2600 0 R (M14.9.19489.sectionxxx.162.Identifier.Acceptance.Filter) 2601 0 R (M14.9.19498.Table.Title.Table.82.RISC.Controller.Configuration.Register) 2602 0 R (M14.9.19641.sectionxxxx.1711.MSCAN.Control.0.Register.CANCTL0) 2603 0 R (M14.9.20683.sectionxxxx.1612.Receive.Structures) 2604 0 R (M14.9.21455.FigTitle.Figure13.MSCAN.Control.Register.0.CANCTL0) 2605 0 R (M14.9.21573.sectionxxxx.1613.Transmit.Structures) 2606 0 R (M14.9.21983.sectionxxx.622.Receive.Interrupt) 2607 0 R (M14.9.22787.sectionxxxx.1713.MSCAN.Bus.Timing.Register.0.CANBTR0) 2608 0 R (M14.9.22841.Heading4.13213.MSCAN.Reserved.Register) 2609 0 R (M14.9.23438.figuretitle.Figure.14.16bit.Maskable.Acceptance.Filters) 2610 0 R (M14.9.23452.figuretitle.Figure.13.32bit.Maskable.Identifier.Acceptance.Filter) 2611 0 R (M14.9.24288.sectionxxxx.17110.MSCAN.Transmitter.Message.Abort.Control.CANTAB1) 2612 0 R (M14.9.24510.sectionxxxx.1719.MSCAN.Identifier.Acceptance.Control.Register.CANIDAC) 2613 0 R (M14.9.24961.TBTitle.Table126.IDR1.Register.Field.Descriptions) 2614 0 R (M14.9.25139.tabletitle.Table.19.CPU.vs.MSCAN.Operating.Modes) 2615 0 R (M14.9.25169.figuretitle.Figure.11.Pulse.Width.Modulation.Block.Diagram) 2616 0 R (M14.9.25825.tabletitle.Table.12.Baud.rate.prescaler) 2617 0 R (M14.9.26393.section.xx.111.Programmers.Model.of.Message.Storage) 2618 0 R (M14.9.27379.sectionxxxx.1712.MSCAN.Control.1.Register.CANCTL1) 2619 0 R (M14.9.27458.FigTitle.Figure123.ReceiveTransmit.Message.Buffer..Standard.Identifier.Mapping) 2620 0 R (M14.9.28742.tabletitle.Table.14.Time.segment.values) 2621 0 R (M14.9.28817.TBTitle.Table125.IDR0.Register.Field.Descriptions) 2622 0 R (M14.9.28942.tabletitle.Table.17.Data.length.codes) 2623 0 R (M14.9.29061.tabletitle.Table.14.Time.Segment.Values) 2624 0 R (M14.9.29435.sectionxxxx.1715.MSCAN.Receiver.Flag.Register.CANRFLG) 2625 0 R (M14.9.29687.sectionxxx.624.Error.Interrupt) 2626 0 R (M14.9.29818.sectionxxx.164.Clock.System) 2627 0 R (M14.9.29960.sectionxxxx.3324.Transmit.Buffer.Priority.Register.TBPR) 2628 0 R (M14.9.30491.tabletitle.Table.16.Identifier.Acceptance.Hit.Indication) 2629 0 R (M14.9.32607.section.xxx.51210.MSCAN08.Identifier.Acceptance.Registers.CIDAR03) 2630 0 R (M14.9.33308.tabletitle.Table.11.Synchronization.jump.width) 2631 0 R (M14.9.35850.FigTitle.Figure12.CAN.System) 2632 0 R (M14.9.38146.section.xxx.562.Data.Segment.Registers.DSR) 2633 0 R (M14.9.38566.sectionxxx.182.Identifier.Registers.IDRn) 2634 0 R (M14.9.38785.sectionxxx.1115.MSCAN.Soft.Reset.Mode) 2635 0 R (M14.9.39875.sectionxx.112.Low.Power.Options) 2636 0 R] /Limits [(M13.9.65443.tabletitle.Table.35.Sample.Time.Select) (M14.9.39875.sectionxx.112.Low.Power.Options)] >> endobj 62 0 obj << /Names [(M14.9.40403.sectionxxxx.1716.MSCAN.Receiver.Interrupt.Enable.Register.CANRIER) 2637 0 R (M14.9.42747.tabletitle.Table.15.Identifier.Acceptance.Mode.Settings) 2638 0 R (M14.9.45672.FigTitle.Figure123.ReceiveTransmit.Message.Buffer..Extended.Identifier.Mapping) 2639 0 R (M14.9.46780.sectionxxx.161.Message.Storage) 2640 0 R (M14.9.47767.sectionxxxx.1719.MSCAN.Transmitter.Message.Abort.Control.CANTAB0) 2641 0 R (M14.9.48434.FigTitle.Figure13.MSCAN.Register.Summarystatement) 2642 0 R (M14.9.50311.Heading3.144.Modes.of.Operation) 2643 0 R (M14.9.50791.tablenote.1.See.the.Bosch.CAN.20AB.protocol.specification.dated.September.1991.for.a.det) 2644 0 R (M14.9.54673.sectionxxxx.1725.Time.Stamp.Register.TSRH.TSRL) 2645 0 R (M14.9.56739.sectionxxxx.33114.MSCAN.Miscellaneous.Register.CANMISC) 2646 0 R (M14.9.57299.sectionxx.52.BusOff.recovery) 2647 0 R (M14.9.60912.Heading4.1454.MSCAN.Normal.Mode) 2648 0 R (M14.9.63754.Heading2.12.External.Signal.Description) 2649 0 R (M14.9.65122.tabletitle.Table.11.Time.Segment.Syntax) 2650 0 R (M14.9.65216.Heading4.1663.Operation.in.Stop.Mode) 2651 0 R (M14.9.67691.Heading4.1522.MSCAN.Control.Register.0.CANCTL0) 2652 0 R (M14.9.73265.Heading4.1662.Operation.in.Wait.Mode) 2653 0 R (M14.9.73792.sectionxxxx.17111.MSCAN.Transmit.Buffer.Selection.CANTBSEL) 2654 0 R (M14.9.76026.TBHeadC.Revision.Number) 2655 0 R (M14.9.78771.Heading4.13216.MSCAN.Transmit.Error.Counter.CANTXERR) 2656 0 R (M14.9.81217.ChpTitle.Chapter1.Freescales.Scalable.Controller.Area.Network.S12MSCANV3) 2657 0 R (M14.9.89771.ParaBody.The.CANCTL0.register.provides.various.control.bits.of.the.MSCAN.module.as.descr) 2658 0 R (M14.9.95192.Heading3.132.Register.Descriptions) 2659 0 R (M14.9.95881.list1.1.Assert.CANE) 2660 0 R (M14.9.97394.Heading4.13215.MSCAN.Receive.Error.Counter.CANRXERR) 2661 0 R (M14.9.98604.figuretitle.Figure.139.Initialization.RequestAcknowledge.Cycle) 2662 0 R (M14.9.Clock.System) 2663 0 R (M14.9.Data.Length.Register) 2664 0 R (M14.9.Error.Interrupt) 2665 0 R (M14.9.Identifier.Acceptance.Filter) 2666 0 R (M14.9.Identifier.Registers) 2667 0 R (M14.9.InterFrame.Sequence) 2668 0 R (M14.9.Interrupt.Acknowledge) 2669 0 R (M14.9.ListenOnly.Mode) 2670 0 R (M14.9.Low.Power.Options) 2671 0 R (M14.9.Message.Storage) 2672 0 R (M14.9.Protocol.Violation.Protection) 2673 0 R (M14.9.Receive.Interrupt) 2674 0 R (M14.9.Receive.Structures) 2675 0 R (M14.9.Reset.Initialization) 2676 0 R (M14.9.Time.Stamp.Register) 2677 0 R (M14.9.Transmit.Buffer.Priority.Register) 2678 0 R (M14.9.Transmit.Interrupt) 2679 0 R (M14.9.Transmit.Structures) 2680 0 R (M14.9.WakeUp.Interrupt) 2681 0 R (M15.9.11462.FigTitle.Figure119.PIT24B4C.Detailed.Block.Diagram) 2682 0 R (M15.9.14628.sectionx.Section.4.Functional.Description) 2683 0 R (M15.9.42137.FigTitle.Figure11.PIT24B4C.Block.Diagram) 2684 0 R (M15.9.52665.ChpTitle.Chapter3.Block.Title.Block.Guide) 2685 0 R (M15.9.70126.sectionx.Section.1.Introduction) 2686 0 R (M15.9.89278.figuretitle.Figure.23.PIT.Trigger.Signal.Timing) 2687 0 R (M16.9.10899.sectionxxxx.33112.PWM.Channel.Counter.Registers.PWMCNTx) 2688 0 R (M16.9.11227.figuretitlewide.Figure.16.PWM.Center.Aligned.Output) 2689 0 R (M16.9.13729.sectionx.Section.3.Memory.Map.and.Registers) 2690 0 R (M16.9.14005.figuretitlewide.Figure.14.PWM.Left.Aligned.Output.Block.Diagram) 2691 0 R (M16.9.14628.sectionx.Section.4.Functional.Description) 2692 0 R (M16.9.15238.sectionxxxx.1525.Left.Aligned.Outputs) 2693 0 R (M16.9.16944.sectionxxxx.1526.Center.Aligned.Outputs) 2694 0 R (M16.9.20358.figuretitle.Figure.17.16Bit.PWM.Mode) 2695 0 R (M16.9.22788.sectionxxxx.1521.PWM.Enable) 2696 0 R (M16.9.28530.figuretitlewide.Figure.13..Block.Diagram.of.PWM.Clock.Selects) 2697 0 R (M16.9.31429.sectionxx.14.Block.Diagram) 2698 0 R (M16.9.34409.sectionxxxx.1523.PWM.Period.and.Duty) 2699 0 R (M16.9.35205.TableFootnote.1.Counter.does.not.count) 2700 0 R] /Limits [(M14.9.40403.sectionxxxx.1716.MSCAN.Receiver.Interrupt.Enable.Register.CANRIER) (M16.9.35205.TableFootnote.1.Counter.does.not.count)] >> endobj 63 0 obj << /Names [(M16.9.35700.sectionxxx.151.PWM.Clock.Selects) 2701 0 R (M16.9.36258.sectionxxxx.1528.PWM.Boundary.Cases) 2702 0 R (M16.9.36596.FigTitle.Figure123.PWM.Center.Aligned.Output.Example.Waveform) 2703 0 R (M16.9.37374.TBTitle.Table17.Clock.A.Prescaler.Selects) 2704 0 R (M16.9.37570.sectionxxxx.1527.PWM.16Bit.Functions) 2705 0 R (M16.9.39370.figuretitlewide.Figure.14.PWM.Timer.Channel.Block.Diagram) 2706 0 R (M16.9.40502.TBTitle.Table112.16bit.Concatenation.Mode.Summary) 2707 0 R (M16.9.42223.sectionxxxx.1524.PWM.Timer.Counters) 2708 0 R (M16.9.52665.ChpTitle.Chapter3.Block.Title.Block.Guide) 2709 0 R (M16.9.56108.TBTitle.Table16.Clock.B.Prescaler.Selects) 2710 0 R (M16.9.64154.figuretitle.Figure.11.PWM8B8C.Block.Diagram) 2711 0 R (M16.9.79468.TBTitle.Table113.PWM.Boundary.Cases) 2712 0 R (M16.9.81047.TableFootnote.1.Intended.for.factory.test.purposes.only) 2713 0 R (M16.9.82364.FigTitle.Figure121.PWM.Left.Aligned.Output.Example.Waveform) 2714 0 R (M16.9.82420.sectionxxxx.33115.PWM.Shutdown.Register.PWMSDN) 2715 0 R (M16.9.83969.Heading2.14.Register.Descriptions) 2716 0 R (M17.9.13365.figuretitle.Figure.41.SCI.Block.Diagram) 2717 0 R (M17.9.13729.sectionx.Section.3.Memory.Map.and.Registers) 2718 0 R (M17.9.13922.figuretitlewide.Figure.43.Receiver.Data.Sampling) 2719 0 R (M17.9.14341.figuretitlewide.Figure.47.Start.Bit.Search.Example.4) 2720 0 R (M17.9.14628.sectionx.Section.4.Functional.Description) 2721 0 R (M17.9.14780.figuretitlewide.Figure.49.Start.Bit.Search.Example.6) 2722 0 R (M17.9.15263.sectionxx.33.Register.Descriptions) 2723 0 R (M17.9.15963.tabletitle.Table.44.Start.Bit.Verification) 2724 0 R (M17.9.24202.tablenote.1.Details) 2725 0 R (M17.9.25573.figuretitle.Figure.41.SCI.Data.Formats) 2726 0 R (M17.9.26164.figuretitlewide.Figure.44.Start.Bit.Search.Example.1) 2727 0 R (M17.9.28709.figuretitlewide.Figure.411.Fast.Data) 2728 0 R (M17.9.29574.figuretitlewide.Figure.410.Slow.Data) 2729 0 R (M17.9.30940.tabletitle.Table.71.Reset.Summary) 2730 0 R (M17.9.32067.tabletitle.Table.46.Stop.Bit.Recovery) 2731 0 R (M17.9.32473.tabletitle.Table.45.Data.Bit.Recovery) 2732 0 R (M17.9.33119.tabletitle.Table.43.Baud.Rates.Module.Clock..102.Mhz) 2733 0 R (M17.9.33991.figuretitlewide.Figure.45.Start.Bit.Search.Example.2) 2734 0 R (M17.9.34286.figuretitlewide.Figure.48.Start.Bit.Search.Example.5) 2735 0 R (M17.9.35234.tabletitle.Table.32.Loop.Functions) 2736 0 R (M17.9.36982.figuretitlewide.Figure.46.Start.Bit.Search.Example.3) 2737 0 R (M17.9.41025.FigTitle.Figure117.Break.Detection.if.BRKDFE..1M0) 2738 0 R (M17.9.43225.Heading4.1553.Break.Characters) 2739 0 R (M17.9.51844.figuretitle.Figure.46.Timing.Diagram.Bit.Error.Detection) 2740 0 R (M17.9.52366.FigTitle.Figure11.SCI.Block.Diagram) 2741 0 R (M17.9.52665.ChpTitle.Chapter3.Block.Title.Block.Guide) 2742 0 R (M17.9.56094.figuretitlewide.Figure.46.Start.Bit.Search.Example.2) 2743 0 R (M17.9.58369.figuretitlewide.Figure.48.Start.Bit.Search.Example.4) 2744 0 R (M17.9.58780.sectionxxx.462.Character.Transmission) 2745 0 R (M17.9.59396.figuretitlewide.Figure.45.Start.Bit.Search.Example.1) 2746 0 R (M17.9.62636.TBTitle.Table13.IRSCI.Transmit.Pulse.Width) 2747 0 R (M17.9.68027.TBTitle.Table119.Stop.Bit.Recovery) 2748 0 R (M17.9.68234.figuretitlewide.Figure.411.Slow.Data) 2749 0 R (M17.9.70126.sectionx.Section.1.Introduction) 2750 0 R (M17.9.70572.figuretitlewide.Figure.47.Start.Bit.Search.Example.3) 2751 0 R (M17.9.70641.TBTitle.Table118.Data.Bit.Recovery) 2752 0 R (M17.9.72308.Heading4.1466.Receiver.Wakeup) 2753 0 R (M17.9.81016.TBTitle.Table19.Bit.Error.Mode.Coding) 2754 0 R (M17.9.87272.figuretitlewide.Figure.412.Fast.Data) 2755 0 R (M17.9.89864.TBTitle.Table15.SCICR1.Field.Descriptions) 2756 0 R (M17.9.91871.body.Figure.11.is.a.high.level.block.diagram.of.SCI.module.showing.the.interaction.of.va) 2757 0 R (M17.9.98205.FigTitle.Figure12.SCI.Register.Summary) 2758 0 R (M17.9.99306.figuretitlewide.Figure.410.Start.Bit.Search.Example.6) 2759 0 R (M18.9.11636.sectionxxx.334.SPI.Status.Register) 2760 0 R (M18.9.11999.TBTitle.Table19.SPIF.Interrupt.Flag.Clearing.Sequence) 2761 0 R (M18.9.12038.figuretitlewide.Figure.33.SPI.Clock.Format.0.CPHA..0) 2762 0 R (M18.9.13059.sectionxx.38.Transmission.Formats) 2763 0 R (M18.9.13729.sectionx.Section.3.Memory.Map.and.Registers) 2764 0 R] /Limits [(M16.9.35700.sectionxxx.151.PWM.Clock.Selects) (M18.9.13729.sectionx.Section.3.Memory.Map.and.Registers)] >> endobj 64 0 obj << /Names [(M18.9.14628.sectionx.Section.4.Functional.Description) 2765 0 R (M18.9.14694.tabletitle.Table.34) 2766 0 R (M18.9.14905.sectionxxx.342.SPI.Control.Register.2) 2767 0 R (M18.9.16396.Paranote.1.n.depends.on.the.selected.transfer.width.please.refer.to.Section1322.SPI.Cont) 2768 0 R (M18.9.17571.figuretitle.Figure.37.Receiption.with.SPIF.serviced.to.late.Data.B.is.lost) 2769 0 R (M18.9.19715.sectionxx.48.Low.Power.Mode.Options) 2770 0 R (M18.9.21812.figuretitlewide.Figure.34.SPI.Clock.Format.1.CPHA..1) 2771 0 R (M18.9.23635.tabletitle.Table.32.SS.Output.Selection) 2772 0 R (M18.9.23927.sectionxx.49.Errata) 2773 0 R (M18.9.31907.TableFootnote.1.Any.write.to.SPIDRH.or.SPIDRL.with.SPTEF..0.is.effectively.ignored) 2774 0 R (M18.9.33466.FigTitle.Figure11.SPI.Block.Diagram) 2775 0 R (M18.9.37529.Heading3.2132.Register.Descriptions) 2776 0 R (M18.9.38133.FigTitle.Figure12.SPI.Register.Summary) 2777 0 R (M18.9.41504.tabletitle.Table.41.Normal.Mode.and.Bidirectional.Mode) 2778 0 R (M18.9.42829.BitNumber.7) 2779 0 R (M18.9.44399.Paranote.1.n.depends.on.the.selected.transfer.width.please.refer.to.Section1322.SPI.Cont) 2780 0 R (M18.9.52665.ChpTitle.Chapter3.Block.Title.Block.Guide) 2781 0 R (M18.9.53546.Equation.Eqn13.BaudRateDivisor..SPPR..1..2SPR..1) 2782 0 R (M18.9.58287.TBTitle.Table110.SPTEF.Interrupt.Flag.Clearing.Sequence) 2783 0 R (M18.9.70126.sectionx.Section.1.Introduction) 2784 0 R (M18.9.73849.tabletitle.Table.33.Bidirectional.Pin.Configurations) 2785 0 R (M18.9.88435.TableFootnote.1.n.is.used.later.in.this.document.as.a.placeholder.for.the.selected.trans) 2786 0 R (M18.9.98749.figuretitle.Figure.36.Receiption.with.SPIF.serviced.in.time) 2787 0 R (M19.9.13729.sectionx.Section.3.Memory.Map.and.Registers) 2788 0 R (M19.9.14745.TBTitle.Table110.The.OC7.and.OCx.event.priority) 2789 0 R (M19.9.15712.TBTitle.Table118.Pin.Action) 2790 0 R (M19.9.17017.Heading4.1324.Output.Compare.7.Data.Register.OC7D) 2791 0 R (M19.9.18057.TBTitle.Table119.Timer.Clock.Selection) 2792 0 R (M19.9.18751.Heading4.13216.Pulse.Accumulator.Flag.Register.PAFLG) 2793 0 R (M19.9.19433.Heading4.1328.Timer.Control.Register.1Timer.Control.Register.2.TCTL1TCTL2) 2794 0 R (M19.9.19876.figuretitle.Figure.41.Detailed.Timer.Block.Diagram) 2795 0 R (M19.9.20788.Heading4.13215.16Bit.Pulse.Accumulator.Control.Register.PACTL) 2796 0 R (M19.9.26008.Heading3.112.Modes.of.Operation) 2797 0 R (M19.9.26479.tabletitle.Table.39.Timer.New.Prescalar.Selection) 2798 0 R (M19.9.26945.TBTitle.Table123.Precision.Timer.Prescaler.Selection.Examples.when.PRNT..1) 2799 0 R (M19.9.28010.Heading4.22323.Output.Compare.7.Mask.Register.OC7M) 2800 0 R (M19.9.31284.Heading4.13219.Precision.Timer.Prescaler.Select.Register.PTPSR) 2801 0 R (M19.9.31873.Heading2.18.Interrupts) 2802 0 R (M19.9.34875.TBTitle.Table114.Timer.Clock.Selection) 2803 0 R (M19.9.40067.Heading4.13213.Main.Timer.Interrupt.Flag.2.TFLG2) 2804 0 R (M19.9.43202.Heading4.13211.Timer.System.Control.Register.2.TSCR2) 2805 0 R (M19.9.46753.Heading3.2232.Register.Descriptions) 2806 0 R (M19.9.50708.Heading4.13212.Main.Timer.Interrupt.Flag.1.TFLG1) 2807 0 R (M19.9.51071.TBTitle.Table121.TIM16B8CV1.Interrupts) 2808 0 R (M19.9.52414.FigTitle.Figure132.The.TCNT.cycle.diagram.under.TCRE1.condition) 2809 0 R (M19.9.52665.ChpTitle.Chapter3.Block.Title.Block.Guide) 2810 0 R (M19.9.78099.Heading3.143.Output.Compare) 2811 0 R (M19.9.83074.tabletitle.Table.61.Interrupts) 2812 0 R (M19.9.86529.Heading3.142.Input.Capture) 2813 0 R (M19.9.88775.FigTitle.Figure134.16Bit.Pulse.Accumulator.Control.Register.PACTL) 2814 0 R (M19.9.95590.FigTitle.Figure16.TIM16B8CV2.Register.Summary) 2815 0 R (M19.9.99882.Heading4.1322.Timer.Compare.Force.Register.CFORC) 2816 0 R (M20.9.23058.sectionxx.13.Modes.of.Operation) 2817 0 R (M20.9.23348.tabletitle.Table.11.Reset.Summary) 2818 0 R (M20.9.25552.FigTitle.Figure11.Block.Diagram) 2819 0 R (M20.9.29728.sectionx.Section.3.Memory.Map.and.Registers) 2820 0 R (M20.9.31429.sectionxx.14.Block.Diagram) 2821 0 R (M20.9.34589.TBTitle.Table112.Trimming.Effect.of.APIT) 2822 0 R (M20.9.35703.TBTitle.Table16.Trimming.Effect.of.APIT) 2823 0 R (M20.9.36518.figuretitle.Figure.31.VREG3V3.Control.Register.CTRL) 2824 0 R (M20.9.39706.sectionxx.48.API..Autonomous.Periodical.Interrupt) 2825 0 R (M20.9.44125.TBTitle.Table222.Register.Summary) 2826 0 R (M20.9.52665.ChpTitle.Chapter3.Block.Title.Block.Guide) 2827 0 R (M20.9.57950.sectionxxx.331.VREG3V3..HT.Control.Register.VREGHTCL) 2828 0 R] /Limits [(M18.9.14628.sectionx.Section.4.Functional.Description) (M20.9.57950.sectionxxx.331.VREG3V3..HT.Control.Register.VREGHTCL)] >> endobj 65 0 obj << /Names [(M20.9.58451.Heading4.1323.Autonomous.Periodical.Interrupt.Control.Register.VREGAPICL) 2829 0 R (M20.9.68563.sectionxx.45.LVR..Low.Voltage.Reset) 2830 0 R (M20.9.82094.TBTitle.Table110.Interrupt.Vectors) 2831 0 R (M20.9.90082.sectionxx.46.HTD..High.Temperature.Detect) 2832 0 R (M20.9.91398.TBTitle.Table11.Signal.Properties) 2833 0 R (M20.9.94110.tabletitle.Table.33.VREG3V3..Selectable.Autonomous.Periodical.Interrupt.Periods) 2834 0 R (M20.9.98478.figuretitle.Figure.11.VREG.Block.Diagram) 2835 0 R (M21.9.10731.TBTitle.Table120.XTAL.Frequency.vs.FDIV) 2836 0 R (M21.9.10794.FigTitle.Figure112.PFlash.Memory.Map.for.FTM256K1) 2837 0 R (M21.9.10995.tabletitle.Table.33.Security.States) 2838 0 R (M21.9.11440.sectionxx.43.Stop.Mode) 2839 0 R (M21.9.11675.Heading4.14410.Data.Flash.Enable.Command) 2840 0 R (M21.9.12505.Heading4.14516.Set.User.Margin.Level.Command) 2841 0 R (M21.9.14138.sectionx.Section.1.Introduction) 2842 0 R (M21.9.14402.sectionxxx.475.Unsecuring.the.Flash.in.Special.Single.Chip.Mode.via.the.BDM) 2843 0 R (M21.9.16147.FigTitle.Figure1192.Generic.Flash.Command.Write.Sequence.Flowchart.for.FTM.FTMR) 2844 0 R (M21.9.16769.Heading3.193.Unsecuring.the.MCU.Using.Backdoor.Key.Access) 2845 0 R (M21.9.17344.sectionxx.32.Module.Memory.Map) 2846 0 R (M21.9.18985.sectionxxx.335.FSTAT..Flash.Status.Register) 2847 0 R (M21.9.19020.TableFootnote.2.Read.margin.to.the.programmed.state) 2848 0 R (M21.9.1931472.tablenote.1931472) 2849 0 R (M21.9.1931475.tablenote.1931475) 2850 0 R (M21.9.1931478.tablenote.1931478) 2851 0 R (M21.9.21261.TableFootnote.1.A.tbl124.MMCCTL1.register.bit) 2852 0 R (M21.9.21452.Heading4.14315.Set.Field.Margin.Level.Command) 2853 0 R (M21.9.22242.TBTitle.Table160.Flash.Commands.by.Mode) 2854 0 R (M21.9.23914.Heading4.14316.Data.Flash.Program.Command) 2855 0 R (M21.9.24092.sectionxxx.333.NVTSTMOD..Test.Mode.Register) 2856 0 R (M21.9.24629.Heading4.1436.Program.Once.Command) 2857 0 R (M21.9.27662.sectionxxxx.4232.Program.and.Erase.Sequences) 2858 0 R (M21.9.28424.sectionxx.12.Features) 2859 0 R (M21.9.29480.Heading4.1328.Error.Status.Register.ERRSTAT) 2860 0 R (M21.9.31429.sectionxx.14.Block.Diagram) 2861 0 R (M21.9.31470.Heading4.1459.Erase.Sector.Command) 2862 0 R (M21.9.32392.sectionxxx.331.CLKDIV..Clock.Divider.Register) 2863 0 R (M21.9.33183.TBTitle.Table15.PFlash.Memory.Addressing.for.FTM256K1) 2864 0 R (M21.9.34016.figuretitle.Figure.38.Flash.Protection.Register.FPROT) 2865 0 R (M21.9.34492.tabletitle.Table.41.Valid.Flash.Commands) 2866 0 R (M21.9.35474.TableFootnote.1.FDIV.shown.generates.an.FCLK.frequency.of.08.MHz) 2867 0 R (M21.9.36997.tabletitle.Table.34.KEYEN.states) 2868 0 R (M21.9.38471.sectionx.Section.6.Interrupts) 2869 0 R (M21.9.39408.tabletitle.Table.36.Flash.Protection.Function) 2870 0 R (M21.9.39831.Heading4.1468.Erase.All.Blocks.Command) 2871 0 R (M21.9.40084.TBTitle.Table196.Erase.Flash.Block.Command.Error.Handling..FTMR.FTMRC) 2872 0 R (M21.9.41598.FigTitle.Figure142.DFlash.Protection.Register.DFPROT) 2873 0 R (M21.9.41931.TBTitle.Table173.Valid.User.Margin.Levels) 2874 0 R (M21.9.42709.tabletitle.Table.35.Higher.Address.Range.Protection) 2875 0 R (M21.9.42727.TBTitle.Table121.FCCOB..NVM.Command.Mode) 2876 0 R (M21.9.44126.Heading4.14310.Erase.Flash.Block.Command..FTMR.FTMRC) 2877 0 R (M21.9.45355.ChpTitle.Chapter1.256.KByte.Flash.Module.S12XFTMR256K1V1) 2878 0 R (M21.9.45998.tabletitle.Table.39.Allowed.Flash.Protection.Scenario.Transitions) 2879 0 R (M21.9.46321.Heading4.13213.Flash.ECC.Error.Results.Register.FECCR) 2880 0 R (M21.9.47067.figuretitle.Figure.310.Flash.Security.Register.FSEC) 2881 0 R (M21.9.47591.TBTitle.Table157.Valid.Field.Margin.Levels) 2882 0 R (M21.9.47674.FigTitle.Figure129.Flash.Option.Register.FOPT..NVM.User.Mode) 2883 0 R (M21.9.49497.tabletitle.Table.325.Flash.Protection.Lower.Address.Range.FTS128K1.FTS128K1ECC) 2884 0 R (M21.9.54636.Heading4.1455.Program.Command) 2885 0 R (M21.9.56065.sectionxxx.338.RESERVED1FCTL..Flash.Control.Register) 2886 0 R (M21.9.56119.TableFootnote.2.Reset.value.can.deviate.from.the.value.shown.if.a.double.fault.is.detect) 2887 0 R (M21.9.56253.TableFootnote.1.Read.margin.to.the.erased.state) 2888 0 R (M21.9.57215.sectionxxx.111.Glossary) 2889 0 R (M21.9.60379.Heading3.155.Mode.and.Security.Effects.on.Flash.Command.Availability) 2890 0 R (M21.9.60634.Heading4.14612.Unsecure.Flash.Command) 2891 0 R (M21.9.63735.TableFootnote.1.0x7FF08..0x7FFF0F.form.a.Flash.phase.and.must.be.programmed.in.a.single.) 2892 0 R] /Limits [(M20.9.58451.Heading4.1323.Autonomous.Periodical.Interrupt.Control.Register.VREGAPICL) (M21.9.63735.TableFootnote.1.0x7FF08..0x7FFF0F.form.a.Flash.phase.and.must.be.programmed.in.a.single.)] >> endobj 66 0 obj << /Names [(M21.9.64104.sectionxx.41.Program.and.Erase.Operation) 2893 0 R (M21.9.64585.Heading4.14317.Verify.Backdoor.Access.Key.Command) 2894 0 R (M21.9.66585.FigTitle.Figure1192.Flash.Module.Interrupts.Implementation..FTMR) 2895 0 R (M21.9.66807.Heading4.1326.Flash.Error.Configuration.Register.FERCNFG) 2896 0 R (M21.9.68147.Heading4.1436.Program.PFlash.Command) 2897 0 R (M21.9.69927.sectionxxxx.3351.Flash.Protection.Restrictions) 2898 0 R (M21.9.70712.Heading2.13.Memory.Map.and.Registers) 2899 0 R (M21.9.708541.tablenote.708541) 2900 0 R (M21.9.71423.figuretitle.Figure.343.Flash.Protection.Scenarios.for.FTS512K4FTS512K4ECC) 2901 0 R (M21.9.71582.Heading3.145.Flash.Command.Details) 2902 0 R (M21.9.71963.TBTitle.Table11.FTMRC.Revision.History) 2903 0 R (M21.9.73133.FigTitle.Figure16.FTM1024K5.Register.Summary.Normal.Mode) 2904 0 R (M21.9.73293.TBTitle.Table141.DFlash.Protection.Address.Range) 2905 0 R (M21.9.75018.Heading2.14.Functional.Description) 2906 0 R (M21.9.75860.tabletitle.Table.31.Flash.ProtectionOptions.Field) 2907 0 R (M21.9.76683.TBTitle.Table111.FECCERR.Index.Settings) 2908 0 R (M21.9.78480.Heading4.1443.Valid.Flash.Module.Commands) 2909 0 R (M21.9.78783.Heading4.13211.DFlash.Protection.Register.DFPROT..FTMR) 2910 0 R (M21.9.78986.sectionxxxx.4261.Writing.the.CLKDIV.Register) 2911 0 R (M21.9.79922.FigTitle.Figure13.FTM256K1.Block.Diagram) 2912 0 R (M21.9.80558.sectionxxx.335.FPROT..Flash.Protection.Register) 2913 0 R (M21.9.80615.Heading2.110.Flash.Module.Security) 2914 0 R (M21.9.82798.sectionxxx.332.NVOPT..Option.Register) 2915 0 R (M21.9.86523.TBTitle.Table171.DFlash.Commands) 2916 0 R (M21.9.90012.Heading4.1324.Flash.ECCR.Index.Register.FECCRIX) 2917 0 R (M21.9.91491.sectionxx.33.Register.Descriptions) 2918 0 R (M21.9.91886.Heading3.144.Data.Flash.Commands) 2919 0 R (M21.9.92923.Heading4.1123.DFlash.Features) 2920 0 R (M21.9.93992.TBTitle.Table15.PFlash.IFR.Block.0N.Fields) 2921 0 R (M21.9.94529.Heading2.16.Initialization) 2922 0 R (M21.9.94796.Heading4.1438.Read.Once.Command) 2923 0 R (M21.9.95115.Heading5.111368.Backdoor.Key.access.Command) 2924 0 R (M21.9.95934.sectionxxx.333.CNFG..Configuration.Register) 2925 0 R (M21.9.97264.TableFootnote.2.FDIV.shown.generates.an.FCLK.frequency.of.105.MHz) 2926 0 R (M21.9.98290.sectionxxx.339.FCMD..Flash.Command.Buffer.and.Register) 2927 0 R (M21.9.99984.Heading4.1121.PFlash.Features) 2928 0 R (M21.9.Command.Write.Sequence) 2929 0 R (M22.9.10731.TBTitle.Table120.XTAL.Frequency.vs.FDIV) 2930 0 R (M22.9.10995.tabletitle.Table.33.Security.States) 2931 0 R (M22.9.11440.sectionxx.43.Stop.Mode) 2932 0 R (M22.9.11675.Heading4.14410.Data.Flash.Enable.Command) 2933 0 R (M22.9.12505.Heading4.14516.Set.User.Margin.Level.Command) 2934 0 R (M22.9.14138.sectionx.Section.1.Introduction) 2935 0 R (M22.9.14402.sectionxxx.475.Unsecuring.the.Flash.in.Special.Single.Chip.Mode.via.the.BDM) 2936 0 R (M22.9.16147.FigTitle.Figure1192.Generic.Flash.Command.Write.Sequence.Flowchart.for.FTM.FTMR) 2937 0 R (M22.9.16769.Heading3.193.Unsecuring.the.MCU.Using.Backdoor.Key.Access) 2938 0 R (M22.9.17344.sectionxx.32.Module.Memory.Map) 2939 0 R (M22.9.18985.sectionxxx.335.FSTAT..Flash.Status.Register) 2940 0 R (M22.9.19020.TableFootnote.2.Read.margin.to.the.programmed.state) 2941 0 R (M22.9.1931472.tablenote.1931472) 2942 0 R (M22.9.1931475.tablenote.1931475) 2943 0 R (M22.9.1931478.tablenote.1931478) 2944 0 R (M22.9.21261.TableFootnote.1.A.tbl124.MMCCTL1.register.bit) 2945 0 R (M22.9.21452.Heading4.14315.Set.Field.Margin.Level.Command) 2946 0 R (M22.9.22242.TBTitle.Table160.Flash.Commands.by.Mode) 2947 0 R (M22.9.23914.Heading4.14316.Data.Flash.Program.Command) 2948 0 R (M22.9.24092.sectionxxx.333.NVTSTMOD..Test.Mode.Register) 2949 0 R (M22.9.24629.Heading4.1436.Program.Once.Command) 2950 0 R (M22.9.25412.FigTitle.Figure12.FTMR128K1.Block.Diagram) 2951 0 R (M22.9.27662.sectionxxxx.4232.Program.and.Erase.Sequences) 2952 0 R (M22.9.28424.sectionxx.12.Features) 2953 0 R (M22.9.29480.Heading4.1328.Error.Status.Register.ERRSTAT) 2954 0 R (M22.9.31429.sectionxx.14.Block.Diagram) 2955 0 R (M22.9.31470.Heading4.1459.Erase.Sector.Command) 2956 0 R] /Limits [(M21.9.64104.sectionxx.41.Program.and.Erase.Operation) (M22.9.31470.Heading4.1459.Erase.Sector.Command)] >> endobj 67 0 obj << /Names [(M22.9.32392.sectionxxx.331.CLKDIV..Clock.Divider.Register) 2957 0 R (M22.9.34016.figuretitle.Figure.38.Flash.Protection.Register.FPROT) 2958 0 R (M22.9.34492.tabletitle.Table.41.Valid.Flash.Commands) 2959 0 R (M22.9.35474.TableFootnote.1.FDIV.shown.generates.an.FCLK.frequency.of.08.MHz) 2960 0 R (M22.9.36997.tabletitle.Table.34.KEYEN.states) 2961 0 R (M22.9.38471.sectionx.Section.6.Interrupts) 2962 0 R (M22.9.39408.tabletitle.Table.36.Flash.Protection.Function) 2963 0 R (M22.9.39831.Heading4.1468.Erase.All.Blocks.Command) 2964 0 R (M22.9.40084.TBTitle.Table196.Erase.Flash.Block.Command.Error.Handling..FTMR.FTMRC) 2965 0 R (M22.9.40720.TBTitle.Table111.PFlash.Memory.Addressing.for.FTMR128K1) 2966 0 R (M22.9.41598.FigTitle.Figure142.DFlash.Protection.Register.DFPROT) 2967 0 R (M22.9.41931.TBTitle.Table173.Valid.User.Margin.Levels) 2968 0 R (M22.9.42709.tabletitle.Table.35.Higher.Address.Range.Protection) 2969 0 R (M22.9.42727.TBTitle.Table121.FCCOB..NVM.Command.Mode) 2970 0 R (M22.9.44126.Heading4.14310.Erase.Flash.Block.Command..FTMR.FTMRC) 2971 0 R (M22.9.45998.tabletitle.Table.39.Allowed.Flash.Protection.Scenario.Transitions) 2972 0 R (M22.9.46321.Heading4.13213.Flash.ECC.Error.Results.Register.FECCR) 2973 0 R (M22.9.47067.figuretitle.Figure.310.Flash.Security.Register.FSEC) 2974 0 R (M22.9.47591.TBTitle.Table157.Valid.Field.Margin.Levels) 2975 0 R (M22.9.47674.FigTitle.Figure129.Flash.Option.Register.FOPT..NVM.User.Mode) 2976 0 R (M22.9.49497.tabletitle.Table.325.Flash.Protection.Lower.Address.Range.FTS128K1.FTS128K1ECC) 2977 0 R (M22.9.54636.Heading4.1455.Program.Command) 2978 0 R (M22.9.56065.sectionxxx.338.RESERVED1FCTL..Flash.Control.Register) 2979 0 R (M22.9.56119.TableFootnote.2.Reset.value.can.deviate.from.the.value.shown.if.a.double.fault.is.detect) 2980 0 R (M22.9.56253.TableFootnote.1.Read.margin.to.the.erased.state) 2981 0 R (M22.9.57215.sectionxxx.111.Glossary) 2982 0 R (M22.9.60379.Heading3.155.Mode.and.Security.Effects.on.Flash.Command.Availability) 2983 0 R (M22.9.60634.Heading4.14612.Unsecure.Flash.Command) 2984 0 R (M22.9.63735.TableFootnote.1.0x7FF08..0x7FFF0F.form.a.Flash.phase.and.must.be.programmed.in.a.single.) 2985 0 R (M22.9.64104.sectionxx.41.Program.and.Erase.Operation) 2986 0 R (M22.9.64585.Heading4.14317.Verify.Backdoor.Access.Key.Command) 2987 0 R (M22.9.66585.FigTitle.Figure1192.Flash.Module.Interrupts.Implementation..FTMR) 2988 0 R (M22.9.66807.Heading4.1326.Flash.Error.Configuration.Register.FERCNFG) 2989 0 R (M22.9.68147.Heading4.1436.Program.PFlash.Command) 2990 0 R (M22.9.69927.sectionxxxx.3351.Flash.Protection.Restrictions) 2991 0 R (M22.9.70712.Heading2.13.Memory.Map.and.Registers) 2992 0 R (M22.9.708541.tablenote.708541) 2993 0 R (M22.9.71423.figuretitle.Figure.343.Flash.Protection.Scenarios.for.FTS512K4FTS512K4ECC) 2994 0 R (M22.9.71582.Heading3.145.Flash.Command.Details) 2995 0 R (M22.9.71963.TBTitle.Table11.FTMRC.Revision.History) 2996 0 R (M22.9.72237.ChpTitle.Chapter1.128.KByte.Flash.Module.S12XFTMR128K1V1) 2997 0 R (M22.9.73133.FigTitle.Figure16.FTM1024K5.Register.Summary.Normal.Mode) 2998 0 R (M22.9.73293.TBTitle.Table141.DFlash.Protection.Address.Range) 2999 0 R (M22.9.75018.Heading2.14.Functional.Description) 3000 0 R (M22.9.75860.tabletitle.Table.31.Flash.ProtectionOptions.Field) 3001 0 R (M22.9.76683.TBTitle.Table111.FECCERR.Index.Settings) 3002 0 R (M22.9.78480.Heading4.1443.Valid.Flash.Module.Commands) 3003 0 R (M22.9.78783.Heading4.13211.DFlash.Protection.Register.DFPROT..FTMR) 3004 0 R (M22.9.78986.sectionxxxx.4261.Writing.the.CLKDIV.Register) 3005 0 R (M22.9.80558.sectionxxx.335.FPROT..Flash.Protection.Register) 3006 0 R (M22.9.80615.Heading2.110.Flash.Module.Security) 3007 0 R (M22.9.82798.sectionxxx.332.NVOPT..Option.Register) 3008 0 R (M22.9.86523.TBTitle.Table171.DFlash.Commands) 3009 0 R (M22.9.90012.Heading4.1324.Flash.ECCR.Index.Register.FECCRIX) 3010 0 R (M22.9.91491.sectionxx.33.Register.Descriptions) 3011 0 R (M22.9.91886.Heading3.144.Data.Flash.Commands) 3012 0 R (M22.9.92923.Heading4.1123.DFlash.Features) 3013 0 R (M22.9.93992.TBTitle.Table15.PFlash.IFR.Block.0N.Fields) 3014 0 R (M22.9.94529.Heading2.16.Initialization) 3015 0 R (M22.9.94796.Heading4.1438.Read.Once.Command) 3016 0 R (M22.9.95115.Heading5.111368.Backdoor.Key.access.Command) 3017 0 R (M22.9.95934.sectionxxx.333.CNFG..Configuration.Register) 3018 0 R (M22.9.97264.TableFootnote.2.FDIV.shown.generates.an.FCLK.frequency.of.105.MHz) 3019 0 R (M22.9.98171.FigTitle.Figure110.PFlash.Memory.Map.for.FTM128K1) 3020 0 R] /Limits [(M22.9.32392.sectionxxx.331.CLKDIV..Clock.Divider.Register) (M22.9.98171.FigTitle.Figure110.PFlash.Memory.Map.for.FTM128K1)] >> endobj 68 0 obj << /Names [(M22.9.98290.sectionxxx.339.FCMD..Flash.Command.Buffer.and.Register) 3021 0 R (M22.9.99984.Heading4.1121.PFlash.Features) 3022 0 R (M22.9.Command.Write.Sequence) 3023 0 R (M23.9.10731.TBTitle.Table120.XTAL.Frequency.vs.FDIV) 3024 0 R (M23.9.10995.tabletitle.Table.33.Security.States) 3025 0 R (M23.9.11440.sectionxx.43.Stop.Mode) 3026 0 R (M23.9.11675.Heading4.14410.Data.Flash.Enable.Command) 3027 0 R (M23.9.12505.Heading4.14516.Set.User.Margin.Level.Command) 3028 0 R (M23.9.14138.sectionx.Section.1.Introduction) 3029 0 R (M23.9.14402.sectionxxx.475.Unsecuring.the.Flash.in.Special.Single.Chip.Mode.via.the.BDM) 3030 0 R (M23.9.16147.FigTitle.Figure1192.Generic.Flash.Command.Write.Sequence.Flowchart.for.FTM.FTMR) 3031 0 R (M23.9.16769.Heading3.193.Unsecuring.the.MCU.Using.Backdoor.Key.Access) 3032 0 R (M23.9.17344.sectionxx.32.Module.Memory.Map) 3033 0 R (M23.9.18985.sectionxxx.335.FSTAT..Flash.Status.Register) 3034 0 R (M23.9.19020.TableFootnote.2.Read.margin.to.the.programmed.state) 3035 0 R (M23.9.1931472.tablenote.1931472) 3036 0 R (M23.9.1931475.tablenote.1931475) 3037 0 R (M23.9.1931478.tablenote.1931478) 3038 0 R (M23.9.21452.Heading4.14315.Set.Field.Margin.Level.Command) 3039 0 R (M23.9.22242.TBTitle.Table160.Flash.Commands.by.Mode) 3040 0 R (M23.9.23914.Heading4.14316.Data.Flash.Program.Command) 3041 0 R (M23.9.24092.sectionxxx.333.NVTSTMOD..Test.Mode.Register) 3042 0 R (M23.9.24629.Heading4.1436.Program.Once.Command) 3043 0 R (M23.9.27662.sectionxxxx.4232.Program.and.Erase.Sequences) 3044 0 R (M23.9.28424.sectionxx.12.Features) 3045 0 R (M23.9.29480.Heading4.1328.Error.Status.Register.ERRSTAT) 3046 0 R (M23.9.31429.sectionxx.14.Block.Diagram) 3047 0 R (M23.9.31470.Heading4.1459.Erase.Sector.Command) 3048 0 R (M23.9.32392.sectionxxx.331.CLKDIV..Clock.Divider.Register) 3049 0 R (M23.9.34016.figuretitle.Figure.38.Flash.Protection.Register.FPROT) 3050 0 R (M23.9.34492.tabletitle.Table.41.Valid.Flash.Commands) 3051 0 R (M23.9.35474.TableFootnote.1.FDIV.shown.generates.an.FCLK.frequency.of.08.MHz) 3052 0 R (M23.9.36997.tabletitle.Table.34.KEYEN.states) 3053 0 R (M23.9.37064.TableFootnote.1.XAs.found.in.the.memory.map.for.PARENT) 3054 0 R (M23.9.37223.ChpTitle.Chapter1.64.KByte.Flash.Module.S12XFTMR64K1V1) 3055 0 R (M23.9.38132.TableFootnote.2.XAs.found.in.the.memory.map.for.PARENT) 3056 0 R (M23.9.38471.sectionx.Section.6.Interrupts) 3057 0 R (M23.9.39408.tabletitle.Table.36.Flash.Protection.Function) 3058 0 R (M23.9.39538.TableFootnote.2.XAs.found.in.the.memory.map.for.PARENT) 3059 0 R (M23.9.39831.Heading4.1468.Erase.All.Blocks.Command) 3060 0 R (M23.9.40084.TBTitle.Table196.Erase.Flash.Block.Command.Error.Handling..FTMR.FTMRC) 3061 0 R (M23.9.41598.FigTitle.Figure142.DFlash.Protection.Register.DFPROT) 3062 0 R (M23.9.41931.TBTitle.Table173.Valid.User.Margin.Levels) 3063 0 R (M23.9.42709.tabletitle.Table.35.Higher.Address.Range.Protection) 3064 0 R (M23.9.42727.TBTitle.Table121.FCCOB..NVM.Command.Mode) 3065 0 R (M23.9.43942.FigTitle.Figure11.FTMR64K1.Block.Diagram) 3066 0 R (M23.9.44126.Heading4.14310.Erase.Flash.Block.Command..FTMR.FTMRC) 3067 0 R (M23.9.45998.tabletitle.Table.39.Allowed.Flash.Protection.Scenario.Transitions) 3068 0 R (M23.9.46321.Heading4.13213.Flash.ECC.Error.Results.Register.FECCR) 3069 0 R (M23.9.47067.figuretitle.Figure.310.Flash.Security.Register.FSEC) 3070 0 R (M23.9.47591.TBTitle.Table157.Valid.Field.Margin.Levels) 3071 0 R (M23.9.47674.FigTitle.Figure129.Flash.Option.Register.FOPT..NVM.User.Mode) 3072 0 R (M23.9.49497.tabletitle.Table.325.Flash.Protection.Lower.Address.Range.FTS128K1.FTS128K1ECC) 3073 0 R (M23.9.52328.TableFootnote.1.XAs.found.in.the.memory.map.for.PARENT) 3074 0 R (M23.9.54636.Heading4.1455.Program.Command) 3075 0 R (M23.9.56065.sectionxxx.338.RESERVED1FCTL..Flash.Control.Register) 3076 0 R (M23.9.56119.TableFootnote.2.Reset.value.can.deviate.from.the.value.shown.if.a.double.fault.is.detect) 3077 0 R (M23.9.56253.TableFootnote.1.Read.margin.to.the.erased.state) 3078 0 R (M23.9.56680.TBTitle.Table14.PFlash.Memory.Addressing.for.FTMR6K1) 3079 0 R (M23.9.57215.sectionxxx.111.Glossary) 3080 0 R (M23.9.60379.Heading3.155.Mode.and.Security.Effects.on.Flash.Command.Availability) 3081 0 R (M23.9.60634.Heading4.14612.Unsecure.Flash.Command) 3082 0 R (M23.9.63735.TableFootnote.1.0x7FF08..0x7FFF0F.form.a.Flash.phase.and.must.be.programmed.in.a.single.) 3083 0 R (M23.9.64104.sectionxx.41.Program.and.Erase.Operation) 3084 0 R] /Limits [(M22.9.98290.sectionxxx.339.FCMD..Flash.Command.Buffer.and.Register) (M23.9.64104.sectionxx.41.Program.and.Erase.Operation)] >> endobj 69 0 obj << /Names [(M23.9.64585.Heading4.14317.Verify.Backdoor.Access.Key.Command) 3085 0 R (M23.9.66585.FigTitle.Figure1192.Flash.Module.Interrupts.Implementation..FTMR) 3086 0 R (M23.9.66807.Heading4.1326.Flash.Error.Configuration.Register.FERCNFG) 3087 0 R (M23.9.68147.Heading4.1436.Program.PFlash.Command) 3088 0 R (M23.9.69927.sectionxxxx.3351.Flash.Protection.Restrictions) 3089 0 R (M23.9.70712.Heading2.13.Memory.Map.and.Registers) 3090 0 R (M23.9.708541.tablenote.708541) 3091 0 R (M23.9.71423.figuretitle.Figure.343.Flash.Protection.Scenarios.for.FTS512K4FTS512K4ECC) 3092 0 R (M23.9.71582.Heading3.145.Flash.Command.Details) 3093 0 R (M23.9.71963.TBTitle.Table11.FTMRC.Revision.History) 3094 0 R (M23.9.73133.FigTitle.Figure16.FTM1024K5.Register.Summary.Normal.Mode) 3095 0 R (M23.9.73293.TBTitle.Table141.DFlash.Protection.Address.Range) 3096 0 R (M23.9.75018.Heading2.14.Functional.Description) 3097 0 R (M23.9.75860.tabletitle.Table.31.Flash.ProtectionOptions.Field) 3098 0 R (M23.9.76683.TBTitle.Table111.FECCERR.Index.Settings) 3099 0 R (M23.9.78480.Heading4.1443.Valid.Flash.Module.Commands) 3100 0 R (M23.9.78783.Heading4.13211.DFlash.Protection.Register.DFPROT..FTMR) 3101 0 R (M23.9.78986.sectionxxxx.4261.Writing.the.CLKDIV.Register) 3102 0 R (M23.9.80558.sectionxxx.335.FPROT..Flash.Protection.Register) 3103 0 R (M23.9.80615.Heading2.110.Flash.Module.Security) 3104 0 R (M23.9.82798.sectionxxx.332.NVOPT..Option.Register) 3105 0 R (M23.9.86523.TBTitle.Table171.DFlash.Commands) 3106 0 R (M23.9.89235.TableFootnote.1.B.tbl123.MMCCTL1.register.bit) 3107 0 R (M23.9.90012.Heading4.1324.Flash.ECCR.Index.Register.FECCRIX) 3108 0 R (M23.9.91458.TableFootnote.2.XAs.found.in.the.memory.map.for.PARENT) 3109 0 R (M23.9.91491.sectionxx.33.Register.Descriptions) 3110 0 R (M23.9.91886.Heading3.144.Data.Flash.Commands) 3111 0 R (M23.9.92923.Heading4.1123.DFlash.Features) 3112 0 R (M23.9.93992.TBTitle.Table15.PFlash.IFR.Block.0N.Fields) 3113 0 R (M23.9.94090.FigTitle.Figure114.PFlash.Memory.Map.for.FTMR64K1) 3114 0 R (M23.9.94529.Heading2.16.Initialization) 3115 0 R (M23.9.94796.Heading4.1438.Read.Once.Command) 3116 0 R (M23.9.95115.Heading5.111368.Backdoor.Key.access.Command) 3117 0 R (M23.9.95934.sectionxxx.333.CNFG..Configuration.Register) 3118 0 R (M23.9.97264.TableFootnote.2.FDIV.shown.generates.an.FCLK.frequency.of.105.MHz) 3119 0 R (M23.9.98290.sectionxxx.339.FCMD..Flash.Command.Buffer.and.Register) 3120 0 R (M23.9.99159.TableFootnote.1.XAs.found.in.the.memory.map.for.PARENT) 3121 0 R (M23.9.99984.Heading4.1121.PFlash.Features) 3122 0 R (M23.9.Command.Write.Sequence) 3123 0 R (M24.9) 3124 0 R (M24.9.10546.heading2.ATD.Operating.Characteristics) 3125 0 R (M24.9.12580.TableFootnote.1.These.values.include.the.quantization.error.which.is.inherently.12.count) 3126 0 R (M24.9.12587.heading1.ESD.Protection.and.Latchup.Immunity) 3127 0 R (M24.9.18935.heading2.ATD.accuracy) 3128 0 R (M24.9.19667.heading1.Power.Dissipation.and.Thermal.Characteristics) 3129 0 R (M24.9.20432.heading2.POR) 3130 0 R (M24.9.22435.tabletitle.Table.24.0100..010F.Flash.Control.Register.fts256k) 3131 0 R (M24.9.22863.heading1.IO.Characteristics) 3132 0 R (M24.9.22963.tabletitle.Table.33.0280..02FF.CAN4.mscan) 3133 0 R (M24.9.23710.apptabletitle.Table.A16.PLL.Characteristics) 3134 0 R (M24.9.24502.figuretitle.Figure.61.VREG3V3..Chip.Powerup.and.Voltage.Drops) 3135 0 R (M24.9.25336.tablenote.1.Full.accuracy.is.not.guaranteed.when.differential.voltage.is.less.than.475V) 3136 0 R (M24.9.25359.TBTitleApp.TableA11.Run.and.Wait.Current.Characteristics) 3137 0 R (M24.9.26433.tabletitle.Table.113.Operating.conditions) 3138 0 R (M24.9.26792.heading2.Power.Supply) 3139 0 R (M24.9.29412.tabletitle.Table.9.001E.MEBI.section.4.of.4) 3140 0 R (M24.9.30486.tabletitle.Table.271.Recommended.decoupling.capacitor.choice) 3141 0 R (M24.9.31411.tablenote.1.Restrictions.for.oscillator.in.crystal.mode.apply) 3142 0 R (M24.9.31785.TableFootnote.2.Typical.data.retention.values.are.based.on.intrinsic.capability.of.the.t) 3143 0 R (M24.9.32150.tabletitle.Table.29.0180..01BF.CAN1.mscan) 3144 0 R (M24.9.33012.FigTitleApp.FigureA8.SPI.Slave.Timing.CPHA1) 3145 0 R (M24.9.33871.heading2.Factors.influencing.accuracy) 3146 0 R (M24.9.34446.tabletitle.Table.5.0015..0016.INT.section.1.of.2) 3147 0 R (M24.9.35015.TableFootnote.1.TJavg.does.not.exceed.85C.in.a.typical.temperature.profile.over.the.life) 3148 0 R] /Limits [(M23.9.64585.Heading4.14317.Verify.Backdoor.Access.Key.Command) (M24.9.35015.TableFootnote.1.TJavg.does.not.exceed.85C.in.a.typical.temperature.profile.over.the.life)] >> endobj 70 0 obj << /Names [(M24.9.35461.TBTitleApp.TableA16.ATD.Conversion.Performance.5V.range) 3149 0 R (M24.9.35721.TBTitleApp.TableA12.ATD.Operating.Characteristics) 3150 0 R (M24.9.36301.tablenote.2.XCLKS.0.during.reset) 3151 0 R (M24.9.36495.tablenote.2.Please.refer.to.Section.A18.Power.Dissipation.and.Thermal.Characteristics.fo) 3152 0 R (M24.9.37624.apptabletitle.Table.A1.Startup.Characteristics) 3153 0 R (M24.9.37837.appfiguretitle.Figure.A1.ATD.Accuracy.Definitions) 3154 0 R (M24.9.38661.heading1.Operating.conditions) 3155 0 R (M24.9.38732.tabletitle.Table.28.0140..017F.CAN0.mscan) 3156 0 R (M24.9.38750.tabletitle.CAN.Foreground.Receive.and.Foreground.Transmit.Buffer.Layout) 3157 0 R (M24.9.39427.TBTitleApp.TableA11.Pseudo.Stop.and.Full.Stop.Current) 3158 0 R (M24.9.40521.TBTitleApp.TableA10.Module.Run.Supply.Currents) 3159 0 R (M24.9.41373.tabletitle.Table.59.Absolute.Maximum.Ratings) 3160 0 R (M24.9.42072.FigTitleApp.FigureA8.Derating.of.maximum.fSCK.to.fbus.ratio.in.Master.Mode) 3161 0 R (M24.9.42293.TableFootnote.3.These.values.apply.for.carefully.designed.PCB.layouts.with.capacitors.th) 3162 0 R (M24.9.43366.TableFootnote.5.Thermal.characterization.parameter.YJT.is.the.resistance.from.junction.t) 3163 0 R (M24.9.44428.TBTitleApp.TableE2.Peripheral.Options.of.MC9S12XSFamily.Members) 3164 0 R (M24.9.47895.TableFootnote.4.Monitors.VDDX.active.only.in.Full.Performance.Mode.MCU.is.monitored.by.t) 3165 0 R (M24.9.49146.tabletitle.Table.115.5V.IO.Characteristics) 3166 0 R (M24.9.49518.TableFootnote.2.The.device.contains.an.internal.voltage.regulator.to.generate.the.logic.) 3167 0 R (M24.9.49808.heading2.Parameter.Classification) 3168 0 R (M24.9.50559.TBTitleApp.TableA10.Peripheral.Configurations.for.Maximum.Run.Supply.Current) 3169 0 R (M24.9.50870.tabletitle.Table.3.0000..000F.MEBI.section.1.of.4) 3170 0 R (M24.9.54345.apptabletitle.Table.B3.SPI.Slave.Mode.Timing.Characteristics) 3171 0 R (M24.9.55901.heading2.msCAN) 3172 0 R (M24.9.55960.TableFootnote.4.Only.applies.if.EXTAL.is.externally.driven) 3173 0 R (M24.9.56635.heading1.Absolute.Maximum.Ratings) 3174 0 R (M24.9.58244.apptabletitle.Table.A18.Oscillator.Characteristics) 3175 0 R (M24.9.59139.tabletitle.Table.62.VREG3V3..Capacitive.Loads) 3176 0 R (M24.9.59963.appfiguretitle.Figure.B3.SPI.Slave.Timing.CPHA0) 3177 0 R (M24.9.59971.heading1.ATD.Characteristics) 3178 0 R (M24.9.61711.figuretitlewide.Figure.133.Jitter.Definitions) 3179 0 R (M24.9.61728.appfiguretitle.Figure.B1.SPI.Master.Timing.CPHA0) 3180 0 R (M24.9.62501.Heading4App.A222.Source.Resistance) 3181 0 R (M24.9.64660.TBTitleApp.TableA10.Peripheral.Configurations.for.Maximum.Run.Supply.Current) 3182 0 R (M24.9.64999.heading2.Pins) 3183 0 R (M24.9.65493.TableFootnote.1.These.values.include.the.quantization.error.which.is.inherently.12.count) 3184 0 R (M24.9.65720.TBTitleApp.TableA18.NVM.Timing.Characteristics) 3185 0 R (M24.9.67853.tabletitle.Table.91.Measurement.Conditions) 3186 0 R (M24.9.68023.heading2.Current.Injection) 3187 0 R (M24.9.70628.TBTitleApp.TableA17.ATD.Conversion.Performance.33V.range) 3188 0 R (M24.9.72828.tabletitle.Table.8.001C..001D.MMC.section.3.of.4) 3189 0 R (M24.9.72925.tabletitle.Table.27.01200..013F.ATD1.atd10b8c) 3190 0 R (M24.9.73620.TableFootnote.3.TJavg.does.not.exceed.85C.in.a.typical.temperature.profile.over.the.life) 3191 0 R (M24.9.74525.tablenote.1..deviation.from.target.frequency) 3192 0 R (M24.9.78876.tabletitle.Table.32.00240..0027F.PIM.pim9s12dp256) 3193 0 R (M24.9.78883.tabletitle.Table.13.0034..003F.CRG.crg) 3194 0 R (M24.9.79044.TableFootnote.3.Device.functionality.is.guaranteed.on.power.down.to.the.LVR.assert.level) 3195 0 R (M24.9.79853.tabletitle.Table.14.0040..007F.ECT.ect16b8c) 3196 0 R (M24.9.80719.tabletitle.Table.7.0018..001B.Miscellaneous.Peripherals) 3197 0 R (M24.9.80953.heading1.Reset.Oscillator.and.PLL) 3198 0 R (M24.9.81991.AppTitle.AppendixF.Ordering.Information) 3199 0 R (M24.9.82115.TableFootnote.1.fREF..4MHz.fSYS..8MHz.REFDV..00.SYNR..01.XFC.Cs..33nF.Cp..33nF.Rs..27KW) 3200 0 R (M24.9.83824.TableFootnote.1.The.device.contains.an.internal.voltage.regulator.to.generate.the.logic.) 3201 0 R (M24.9.85912.apptabletitle.Table.B2.SPI.Master.Mode.Timing.Characteristics) 3202 0 R (M24.9.86166.TBTitleApp.TableE1.Package.and.Memory.Options.of.MC9S12XSFamily) 3203 0 R (M24.9.86438.AppTitle.AppendixA.Electrical.Characteristics) 3204 0 R (M24.9.87147.appfiguretitle.Figure.B2.SPI.Master.Timing.CPHA1) 3205 0 R (M24.9.87172.TableFootnote.4.Junction.to.case.thermal.resistance.was.simulated.to.be.equivalent.to.th) 3206 0 R (M24.9.88324.tabletitle.Table.19.00D8..00DF.SPI0.spi) 3207 0 R (M24.9.89144.TBTitleApp.TableA13.ATD.Electrical.Characteristics) 3208 0 R (M24.9.90724.sectionxx.16.Detailed.Register.Map) 3209 0 R (M24.9.91906.TBTitleApp.TableA6.33V.IO.Characteristics.ALL.33V.RANGE.IO.PARAMETERS.ARE.SUBJECT.TO.CHA) 3210 0 R (M24.9.92312.heading2.Oscillator) 3211 0 R (M24.9.97758.TableFootnote.2.The.8bit.and.10bit.mode.operation.is.structurally.tested.in.production.t) 3212 0 R] /Limits [(M24.9.35461.TBTitleApp.TableA16.ATD.Conversion.Performance.5V.range) (M24.9.97758.TableFootnote.2.The.8bit.and.10bit.mode.operation.is.structurally.tested.in.production.t)] >> endobj 71 0 obj << /Names [(M24.9.98216.TableFootnote.2.Valid.for.both.Erase.verify.all.or.Erase.verify.block.on.256K.block.with) 3213 0 R (M4.9.13767.tabletitle.Table.12.Assigned.Part.ID.Numbers) 3214 0 R (M4.9.25728.tabletitle.Table.51.Interrupt.Vector.Locations) 3215 0 R (M4.9.33057.Heading3.144.System.States) 3216 0 R (M4.9.40097.sectionxx.41.Overview) 3217 0 R (M4.9.42944.tabletitle.Table.41) 3218 0 R (M4.9.44792.TBTitle.Table12.Derivative.Dependent.Memory.Parameters) 3219 0 R (M4.9.50835.Heading3.111.Features) 3220 0 R (M4.9.51488.tabletitle.Table.91.ATD0.External.Trigger.Sources) 3221 0 R (M4.9.53027.Heading3.1101.Temperature.Sensor.Configuration) 3222 0 R (M4.9.56502.tabletitle.Table.151.Initial.COP.Rate.Configuration) 3223 0 R (M4.9.63899.TBTitle.Table15.Port.Availability.by.Package.Option) 3224 0 R (M4.9.65686.Heading4.12325.PP73..KWP73..PWM73..Port.P.IO.Pins.73) 3225 0 R (M4.9.67510.Heading3.143.Freeze.Mode) 3226 0 R (M4.9.74731.tabletitle.Table.152.Initial.WCOP.Configuration) 3227 0 R (M4.9.76586.TBTitle.Table15.Derivative.Dependent.Flash.Block.Mapping) 3228 0 R (M4.9.77318.sectionxxx.2228.PE7FP22NOACCXCLKS..Port.E.IO.Pin.7) 3229 0 R (M4.9.79199.TBTitle.Table17.Peripheral..Port.Routing.Options) 3230 0 R (M4.9.80392.tabletitle.Table.11.Device.Memory.Map) 3231 0 R (M4.9.83150.TBTitle.Table18.Interrupt.Vector.Locations) 3232 0 R (M4.9.83880.Heading2.111.Oscillator.Configuration) 3233 0 R (M4.9.84223.figuretitle.Figure.31.Clock.Generator) 3234 0 R (M4.9.88720.FigTitle.Figure12.MC9S12XS256.Global.Memory.Map) 3235 0 R (M4.9.88759.tabletitle.Table.41.Mode.selection) 3236 0 R (M4.9.89180.TBTitle.Table111.ATD0.External.Trigger.Sources) 3237 0 R (M4.9.92623.Heading4.1421.System.Stop.Modes) 3238 0 R (M4.9.94021.sectionxxx.434.Register.visibility.in.Emulation.and.Expanded.modes) 3239 0 R (M4.9.94654.FigTitle.Figure11) 3240 0 R (M4.9.94816.tabletitle.Table5.PinOut.Summary) 3241 0 R (M4.9.96166.Heading3.142.Power.Modes) 3242 0 R (M4.9.99260.Heading4.12340.PT30..IOC30..Port.T.IO.Pin.30) 3243 0 R (M4.9.99915.TableFootnote.2.For.compatibility.to.XEfamily) 3244 0 R (M5.9.10306.Heading3.1417.PIM.Reserved.Register) 3245 0 R (M5.9.10378.Heading3.1453.PIM.Reserved.Register) 3246 0 R (M5.9.10801.TBTitle.Table19.Pin.Configuration.Summary) 3247 0 R (M5.9.13169.Heading3.1472.Port.AD.Data.Direction.Register.0.DDR0AD) 3248 0 R (M5.9.13729.sectionx.Section.3.Memory.Map.and.Registers) 3249 0 R (M5.9.16141.TBTitle.Table14.Block.Memory.Map) 3250 0 R (M5.9.16723.Heading3.1452.PIM.Reserved.Register) 3251 0 R (M5.9.17354.FigTitle.Figure17.8Bit.Register.Format) 3252 0 R (M5.9.18884.Heading3.1459.Port.H.Interrupt.Enable.Register.PIEH) 3253 0 R (M5.9.19498.Table.Title.Table.82.RISC.Controller.Configuration.Register) 3254 0 R (M5.9.20326.Heading3.157.PIM.Reserved.Register) 3255 0 R (M5.9.21973.tabletitle.Table.41.Register.availability.per.port) 3256 0 R (M5.9.22846.Heading3.1426.Port.T.Pull.Device.Enable.Register.PERT) 3257 0 R (M5.9.22871.tabletitle.Table.21.Signal.Properties) 3258 0 R (M5.9.23698.tablenote.1.Function.active.during.RESET.only) 3259 0 R (M5.9.24011.Heading3.1462.Port.J.Data.Register.PTJ) 3260 0 R (M5.9.24173.Heading3.1457.Port.H.Reduced.Drive.Register.RDRH) 3261 0 R (M5.9.24771.Heading3.1473.Port.AD.Data.Direction.Register.1.DDR1AD) 3262 0 R (M5.9.25424.Heading3.1475.Port.AD.Reduced.Drive.Register.1.RDR1AD) 3263 0 R (M5.9.26231.Heading3.1436.Port.S.WiredOr.Mode.Register.WOMS) 3264 0 R (M5.9.26458.Heading3.1444.Port.M.WiredOr.Mode.Register.WOMM) 3265 0 R (M5.9.26957.Heading3.1430.Port.S.Data.Register.PTS) 3266 0 R (M5.9.28096.Heading3.1440.Port.M.Data.Direction.Register.DDRM) 3267 0 R (M5.9.30666.tablenote.1.Applicable.only.on.Port.T.S.M.P.H.and.J) 3268 0 R (M5.9.31783.Heading3.1458.Port.H.Polarity.Select.Register.PPSH) 3269 0 R (M5.9.33350.Heading3.151.Memory.Map) 3270 0 R (M5.9.36024.Heading3.1439.Port.M.Input.Register.PTIM) 3271 0 R (M5.9.37109.TBTitle.Table123.PTTRR.Register.Field.Descriptions) 3272 0 R (M5.9.37459.Heading3.1425.Port.T.Reduced.Drive.Register.RDRT) 3273 0 R (M5.9.37716.Heading3.1455.Port.H.Input.Register.PTIH) 3274 0 R (M5.9.38433.Heading3.1476.Port.AD.Pull.Up.Enable.Register.0.PER0AD) 3275 0 R (M5.9.39943.Heading3.1434.Port.S.Pull.Device.Enable.Register.PERS) 3276 0 R] /Limits [(M24.9.98216.TableFootnote.2.Valid.for.both.Erase.verify.all.or.Erase.verify.block.on.256K.block.with) (M5.9.39943.Heading3.1434.Port.S.Pull.Device.Enable.Register.PERS)] >> endobj 72 0 obj << /Names [(M5.9.42540.Heading3.1466.Port.J.Pull.Device.Enable.Register.PERJ) 3277 0 R (M5.9.44631.Heading3.1471.Port.AD.Data.Register.1.PT1AD) 3278 0 R (M5.9.44789.Heading3.144.Port.A.Data.Register.PORTA) 3279 0 R (M5.9.44820.Heading3.1458.Port.H.Pull.Device.Enable.Register.PERH) 3280 0 R (M5.9.45203.Heading3.1422.Port.T.Data.Register.PTT) 3281 0 R (M5.9.45867.Heading4.1421.Data.register.PORTx.PTx) 3282 0 R (M5.9.47196.Heading4.1425.Pull.device.enable.register.PERx) 3283 0 R (M5.9.48095.Heading3.1450.Port.P.Pull.Device.Enable.Register.PERP) 3284 0 R (M5.9.48229.TableFootnote.1.Defaults.to.reset.value) 3285 0 R (M5.9.49108.Heading3.131.Overview) 3286 0 R (M5.9.50156.Heading3.1427.Port.T.Polarity.Select.Register.PPST) 3287 0 R (M5.9.50227.Heading2.15.Functional.Description) 3288 0 R (M5.9.50230.Heading3.1449.Port.P.Reduced.Drive.Register.RDRP) 3289 0 R (M5.9.50415.sectionxx.44.Port.M) 3290 0 R (M5.9.50699.Heading3.1448.Port.P.Data.Direction.Register.DDRP) 3291 0 R (M5.9.50941.Heading3.1437.PIM.Reserved.Register) 3292 0 R (M5.9.51405.Heading3.1413.Port.E.Data.Direction.Register.DDRE) 3293 0 R (M5.9.52012.Heading3.1432.Port.S.Data.Direction.Register.DDRS) 3294 0 R (M5.9.52665.ChpTitle.Chapter3.Block.Title.Block.Guide) 3295 0 R (M5.9.53378.TableFootnote.1.Write.access.not.applicable.for.one.or.more.register.bits.Refer.to.regist) 3296 0 R (M5.9.53715.Heading3.1465.Port.J.Reduced.Drive.Register.RDRJ) 3297 0 R (M5.9.54414.Heading3.1418.IRQ.Control.Register.IRQCR) 3298 0 R (M5.9.54765.Heading3.145.Port.B.Data.Register.PORTB) 3299 0 R (M5.9.55133.Heading3.1441.Port.M.Reduced.Drive.Register.RDRM) 3300 0 R (M5.9.55832.TableFootnote.2.Refer.to.memory.map.in.SoC.Guide.to.determine.related.module) 3301 0 R (M5.9.56677.Heading3.1468.Port.J.Interrupt.Flag.Register.PIFJ) 3302 0 R (M5.9.58586.Heading3.1467.Port.J.Interrupt.Enable.Register.PIEJ) 3303 0 R (M5.9.59271.Heading3.1421.Port.K.Data.Direction.Register.DDRK) 3304 0 R (M5.9.59670.Heading3.1442.Port.M.Pull.Device.Enable.Register.PERM) 3305 0 R (M5.9.60962.Heading3.1470.Port.AD.Data.Register.0.PT0AD) 3306 0 R (M5.9.61262.Heading3.1427.PIM.Reserved.Register) 3307 0 R (M5.9.62770.Heading3.1415.S12XEBI.ports.Reduced.Drive.Register.RDRIV) 3308 0 R (M5.9.63353.Heading3.1574.PIM.Reserved.Registers) 3309 0 R (M5.9.66001.figuretitle.Figure.41.Illustration.of.IO.pin.functionality) 3310 0 R (M5.9.68263.Heading3.1423.Port.T.Input.Register.PTIT) 3311 0 R (M5.9.68330.Heading3.1429.PIM.Reserved.Register) 3312 0 R (M5.9.69104.Heading3.1451.Port.P.Polarity.Select.Register.PPSP) 3313 0 R (M5.9.69274.TBTitle.Table11.Pin.Functions.and.Priorities) 3314 0 R (M5.9.69388.tabletitle.Table.43.Pulse.Detection.Criteria) 3315 0 R (M5.9.70658.Heading3.1456.Port.H.Data.Direction.Register.DDRH) 3316 0 R (M5.9.71097.Heading3.152.Register.Descriptions) 3317 0 R (M5.9.72591.Heading3.1445.PIM.Reserved.Register) 3318 0 R (M5.9.73962.Heading3.1424.Port.T.Data.Direction.Register.DDRT) 3319 0 R (M5.9.75498.Heading3.1446.Port.P.Data.Register.PTP) 3320 0 R (M5.9.75798.Heading3.147.Port.B.Data.Direction.Register.DDRB) 3321 0 R (M5.9.76830.Heading3.1474.Port.AD.Reduced.Drive.Register.0.RDR0AD) 3322 0 R (M5.9.76962.Heading3.1466.Port.J.Polarity.Select.Register.PPSJ) 3323 0 R (M5.9.78424.Heading3.1414.S12XEBI.ports.BKGD.VREGEN.pin.Pullup.Control.Register) 3324 0 R (M5.9.78668.figuretitle.Figure.43.Pulse.Illustration) 3325 0 R (M5.9.80970.figuretitle.Figure.42.Interrupt.Glitch.Filter.on.Port.P.H.and.J.PPS0) 3326 0 R (M5.9.81403.Heading3.1433.Port.S.Reduced.Drive.Register.RDRS) 3327 0 R (M5.9.83135.Heading3.1419.PIM.Reserved.Register) 3328 0 R (M5.9.83748.Heading3.1438.Port.M.Data.Register.PTM) 3329 0 R (M5.9.84367.TableFootnote.1.These.registers.are.reset.to.zero.Two.bus.clock.cycles.after.reset.releas) 3330 0 R (M5.9.84633.Heading3.1431.Port.S.Input.Register.PTIS) 3331 0 R (M5.9.84971.Heading3.1464.Port.J.Data.Direction.Register.DDRJ) 3332 0 R (M5.9.85407.Heading3.1420.Port.K.Data.Register.PORTK) 3333 0 R (M5.9.86591.Heading3.1454.Port.H.Data.Register.PTH) 3334 0 R (M5.9.86739.Heading3.1443.Port.M.Polarity.Select.Register.PPSM) 3335 0 R (M5.9.87489.Heading3.1435.Port.S.Polarity.Select.Register.PPSS) 3336 0 R (M5.9.89265.sectionxx.44.Pin.interrupts) 3337 0 R (M5.9.92794.Heading3.1447.Port.P.Input.Register.PTIP) 3338 0 R (M5.9.92939.Heading3.1416.ECLK.Control.Register.ECLKCTL) 3339 0 R (M5.9.93826.Heading2.31.Introduction) 3340 0 R] /Limits [(M5.9.42540.Heading3.1466.Port.J.Pull.Device.Enable.Register.PERJ) (M5.9.93826.Heading2.31.Introduction)] >> endobj 73 0 obj << /Names [(M5.9.93845.Heading3.1460.Port.H.Interrupt.Flag.Register.PIFH) 3341 0 R (M5.9.93968.TableFootnote.2.Read.always.returns.logic.level.on.pins) 3342 0 R (M5.9.94808.Heading3.1412.Port.E.Data.Register.PORTE) 3343 0 R (M5.9.96528.Heading3.1463.Port.J.Input.Register.PTIJ) 3344 0 R (M5.9.98875.Heading3.1477.Port.AD.Pull.Up.Enable.Register.1.PER1AD) 3345 0 R (M5.9.99326.Heading3.146.Port.A.Data.Direction.Register.DDRA) 3346 0 R (M6.9.12855.tabletitle.Table.104.MCU.Pin.Functions.Related.to.MEBI) 3347 0 R (M6.9.14628.sectionx.Section.4.Functional.Description) 3348 0 R (M6.9.20284.figuretitle.Figure.311.RPAGE.Address.Mapping) 3349 0 R (M6.9.22441.Heading5.14211.Expansion.of.the.Local.Address.Map) 3350 0 R (M6.9.28526.Heading4.1322.Global.Page.Index.Register.GPAGE) 3351 0 R (M6.9.33524.figuretitle.Figure.33.GPAGE.Address.Mapping) 3352 0 R (M6.9.34515.Example.Example11.This.example.demonstrates.usage.of.the.GPAGE.registerstatement) 3353 0 R (M6.9.39034.Heading4.1325.MMC.Control.Register.MMCCTL1) 3354 0 R (M6.9.41263.figuretitle.Figure.41.Logical.to.Global.Address.Mapping) 3355 0 R (M6.9.41649.ChpTitle.Chapter3.Memory.Mapping.Control.S12XMMCV4) 3356 0 R (M6.9.42655.Heading4.3327.Data.FLASH.Page.Index.Register.EPAGE) 3357 0 R (M6.9.44785.FigTitle.Figure16.Mode.Register.MODEfcgipsmode) 3358 0 R (M6.9.47803.FigTitle.Figure123.S12X.CPU..BDM.Global.Address.Mappingfcgs12xcpu.fcgs12xbdm) 3359 0 R (M6.9.59835.figuretitle.Figure.315.PPAGE.Address.Mapping) 3360 0 R (M6.9.61210.tabletitle.Table.42.Implemented.memory.space) 3361 0 R (M6.9.63771.figuretitle.Figure.38.DIRECT.Address.Mapping) 3362 0 R (M6.9.64432.sectionxxxxx.42111.Expansion.of.the.S12XCPU.logical.address.map) 3363 0 R (M6.9.65920.FigTitle.Figure18.Mode.Transition.Diagram.when.MCU.is.Unsecuredfcgipsmode) 3364 0 R (M6.9.71881.figuretitle.Figure.313.EPAGE.Address.Mapping) 3365 0 R (M6.9.74500.figuretitle.Figure.311.DPAGE.Address.Mapping) 3366 0 R (M6.9.78866.FigTitle.Figure127.MMC.Block.Diagramstatement) 3367 0 R (M6.9.79386.Heading4.1423.Implemented.Memory.Map) 3368 0 R (M6.9.81110.FigTitle.Figure12.Quick.Reference.to.MMC.Registers) 3369 0 R (M6.9.91790.figuretitle.Figure.35.Global.Page.Index.Register.GPAGE) 3370 0 R (M6.9.92438.figuretitle.Figure.11.XGATE.Block.Diagram) 3371 0 R (M6.9.95437.sectionxx.51.CALL.and.Return.from.Call.Instructions) 3372 0 R (M6.9.98960.figuretitle.Figure.42.BDMGPR.Address.Mapping) 3373 0 R (M7.9.12207.sectionxxx.311.Interrupt.Vector.Base.Register.IVBR) 3374 0 R (M7.9.13729.sectionx.Section.3.Memory.Map.and.Registers) 3375 0 R (M7.9.14628.sectionx.Section.4.Functional.Description) 3376 0 R (M7.9.22324.Heading4.1531.CPU.Wake.Up.from.Stop.or.Wait.Mode) 3377 0 R (M7.9.23442.tabletitle.Table.32.Interrupt.Priority.Levels) 3378 0 R (M7.9.23761.sectionxxx.312.XGATE.Interrupt.Priority.Configuration.Register.XGINTPRIO) 3379 0 R (M7.9.29005.sectionxxx.314.Service.Request.Configuration.Data.Registers.SRDATA07) 3380 0 R (M7.9.34436.sectionxx.53.Wakeup.from.STOP.or.WAITMode) 3381 0 R (M7.9.35923.figuretitle.Figure.11.INTL8.Block.Diagram) 3382 0 R (M7.9.36232.tabletitle.Table.71.CPU12.Exception.Vector.Map) 3383 0 R (M7.9.39500.Heading3.646.Exception.Priority) 3384 0 R (M7.9.46218.TBTitle.Table11.XINT.Memory.Map) 3385 0 R (M7.9.52665.ChpTitle.Chapter3.Block.Title.Block.Guide) 3386 0 R (M7.9.57633.figuretitle.Figure.51.Interrupt.Processing.example) 3387 0 R (M7.9.63063.tabletitle.Table.33.Interrupt.Priority.Levels) 3388 0 R (M7.9.70126.sectionx.Section.1.Introduction) 3389 0 R (M7.9.72337.Heading3.612.Features) 3390 0 R (M8.9.10246.Figure.title.Figure.1.BDM.Host.to.Target.Serial.Bit.Timing) 3391 0 R (M8.9.11137.tabletitle.Table.31) 3392 0 R (M8.9.13445.sectionxxx.1244.Standard.BDM.Firmware.Commands) 3393 0 R (M8.9.13729.sectionx.Section.3.Memory.Map.and.Registers) 3394 0 R (M8.9.14628.sectionx.Section.4.Functional.Description) 3395 0 R (M8.9.14719.sectionxx.127.Serial.Communication.Timeout) 3396 0 R (M8.9.15744.tabletitle.Table.11..Hardware.Commands1) 3397 0 R (M8.9.19054.sectionxxx.155.BDM.Serial.Interface) 3398 0 R (M8.9.20458.figuretitle.Figure.41.BDM.Command.StructureStatement) 3399 0 R (M8.9.23148.figuretitle.Figure.1215.Startbit.aborts.the.previous.BDC.command) 3400 0 R (M8.9.23353.figuretitle.Figure.121.BDM.Block.Diagram) 3401 0 R (M8.9.25296.notelabel.NOTE) 3402 0 R (M8.9.26058.sectionxxx.161.BDM.Status.Register) 3403 0 R (M8.9.28508.Footnote.2.This.method.is.provided.by.the.Debug.subblockStatement) 3404 0 R] /Limits [(M5.9.93845.Heading3.1460.Port.H.Interrupt.Flag.Register.PIFH) (M8.9.28508.Footnote.2.This.method.is.provided.by.the.Debug.subblockStatement)] >> endobj 74 0 obj << /Names [(M8.9.30933.Figure.title.Figure.3.BDM.Target.to.Host.Serial.Bit.Timing.Logic.0) 3405 0 R (M8.9.34128.tabletitle.Table.12.Firmware.Commands) 3406 0 R (M8.9.34283.sectionxxx.1232.Serial.Interface.Handshake.Abort.Protocol) 3407 0 R (M8.9.35240.sectionxxx.1243.BDM.Hardware.Commands) 3408 0 R (M8.9.36750.sectionxxx.1242.Enabling.and.Activating.BDM) 3409 0 R (M8.9.41588.Figure.title.Figure.2.BDM.Target.to.Host.Serial.Bit.Timing.Logic.1) 3410 0 R (M8.9.52665.ChpTitle.Chapter3.Block.Title.Block.Guide) 3411 0 R (M8.9.56915.sectionxxx.133.LowPower.Modes) 3412 0 R (M8.9.62529.figuretitle.Figure.126.Target.Acknowledge.Pulse.ACK) 3413 0 R (M8.9.70616.sectionxx.41.Security) 3414 0 R (M8.9.70836.tabletitle.Table.31.BDM.Register.Map.Summary) 3415 0 R (M8.9.71489.sectionxx.47.Serial.Interface.Hardware.Handshake.Protocol) 3416 0 R (M8.9.72704.sectionxxx.1261.SYNC..Request.Timed.Reference.Pulse) 3417 0 R (M8.9.76345.tablenote.2.When.the.firmware.command.READNEXT.or.WRITENEXT.is.used.to.access.the.BDM.add) 3418 0 R (M8.9.79115.figuretitle.Figure.1212.ACK.ABORT.and.SYNC.request.Conflict) 3419 0 R (M8.9.80380.figuretitle.Figure.127.Handshake.Protocol.at.Command.Level) 3420 0 R (M8.9.80392.tabletitle.Table.11.Device.Memory.Map) 3421 0 R (M8.9.84835.sectionxx.45.BDM.Command.Structure) 3422 0 R (M9.9.10739.sectionxxx.13414.Breakpoints) 3423 0 R (M9.9.11876.figuretitle.Figure.39.Debug.Control.Register.2.DBGC2) 3424 0 R (M9.9.14083.Heading4.8435.TRIG.Immediate.Trigger) 3425 0 R (M9.9.14628.sectionx.Section.4.Functional.Description) 3426 0 R (M9.9.14977.sectionxxxx.134122.Storing.with.EndTrigger) 3427 0 R (M9.9.15618.sectionxxx.13413.Reading.Data.from.Trace.Buffer) 3428 0 R (M9.9.15655.Heading3.811.Glossary) 3429 0 R (M9.9.16441.sectionxxx.339.Debug.Control.Register.2.DBGC2) 3430 0 R (M9.9.16723.sectionxxx.13411.Storage.Memory) 3431 0 R (M9.9.17455.sectionxxx.13410.Capture.Modes) 3432 0 R (M9.9.19215.Heading5.14522.Loop1.Mode) 3433 0 R (M9.9.20827.FigTitle.Figure123.State.Sequencer.Diagram) 3434 0 R (M9.9.20976.TBTitle.Table136.Comparator.A.and.C.Databus.Consideratins) 3435 0 R (M9.9.22211.TBTitle.Table123) 3436 0 R (M9.9.22505.Heading4.8453.Trace.Buffer.Organization) 3437 0 R (M9.9.23657.tablenote.1.A.word.access.of.ADDRn1.also.accesses.ADDRn.but.does.not.generate.a.match) 3438 0 R (M9.9.23789.sectionxxx.1349.Trigger.Modes) 3439 0 R (M9.9.27174.TBTitle.Table115.ABCM.Encoding) 3440 0 R (M9.9.28335.tabletitle.Table.34.CNT.Decoding.table) 3441 0 R (M9.9.31848.tabletitle.Table.41.Breakpoint.Setup) 3442 0 R (M9.9.33240.sectionxxx.1392.Trigger.Selection) 3443 0 R (M9.9.34075.tabletitle.Table.23) 3444 0 R (M9.9.34521.TBTitle.Table128.Trigger.Priorities) 3445 0 R (M9.9.35821.sectionxx.46.Trace.Modes) 3446 0 R (M9.9.37783.sectionxxxx.134121.Storing.with.BeginTrigger) 3447 0 R (M9.9.38141.figuretitle.Figure.12.DBG12.Block.Diagram.in.Debug.Mode) 3448 0 R (M9.9.39278.figuretitle.Figure.112.Breakpoint.Register.Summary) 3449 0 R (M9.9.39377.TBTitle.Table144.Breakpoint.Setup.For.Both.XGATE.and.S12XCPU.Breakpoints) 3450 0 R (M9.9.39401.Heading4.1423.Range.Comparisons) 3451 0 R (M9.9.45503.sectionxx.32.Comparator.Register.Descriptions) 3452 0 R (M9.9.46039.tabletitle.Table.35.TRCMOD.encoding) 3453 0 R (M9.9.46295.TBTitle.Table17.SSF20..State.Sequence.Flag.Bit.Encoding) 3454 0 R (M9.9.52496.tabletitle.Table.41.Comparator.A.And.C.Databyte.Considerations) 3455 0 R (M9.9.52665.ChpTitle.Chapter3.Block.Title.Block.Guide) 3456 0 R (M9.9.57149.sectionxxx.314.Debug.Comparator.Config.Register.DBGCCR) 3457 0 R (M9.9.57417.sectionxxxx.31101.Debug.Comparator.Control.Register.DBGXCTL) 3458 0 R (M9.9.57756.Heading4.1455.Trace.Buffer.Reset.State) 3459 0 R (M9.9.59640.tabletitle.Table.41) 3460 0 R (M9.9.61021.tabletitle.Table.39.State.Control.Register.Access.Encoding) 3461 0 R (M9.9.65724.Heading4.8423.Data.Bus.Comparison.NDB.Dependency) 3462 0 R (M9.9.66711.Heading4.1327.Debug.State.Control.Registers) 3463 0 R (M9.9.67003.tabletitle.Table.41) 3464 0 R (M9.9.68982.TBTitle.Table137.Comparator.Access.Size.Considerations) 3465 0 R (M9.9.71705.tabletitle.Table.31.DBG.Register.Summary) 3466 0 R (M9.9.72008.TBTitle.Table114.Sample.Glossary.Using.SRS.Terminology) 3467 0 R (M9.9.72171.TBTitle.Table112.TALIGN.Trace.Alignment.Encoding) 3468 0 R] /Limits [(M8.9.30933.Figure.title.Figure.3.BDM.Target.to.Host.Serial.Bit.Timing.Logic.0) (M9.9.72171.TBTitle.Table112.TALIGN.Trace.Alignment.Encoding)] >> endobj 75 0 obj << /Names [(M9.9.76065.sectionxx.44.State.Sequence.Control) 3469 0 R (M9.9.77177.tabletitle.Table.41.Read.or.Write.Comparison.Logic.Table) 3470 0 R (M9.9.78432.TBTitle.Table13.DBGC1.Field.Descriptions) 3471 0 R (M9.9.83252.figuretitle.Figure.11.Debug.Module.Block.Diagram) 3472 0 R (M9.9.86268.FigTitle.Figure11.Debug.Module.Block.Diagram) 3473 0 R (M9.9.89093.TBTitle.Table139.Trace.Buffer.Organization) 3474 0 R (M9.9.90353.Heading4.1476.S12XDBG.Breakpoint.Priorities) 3475 0 R (M9.9.93024.figuretitle.Figure.11) 3476 0 R (M9.9.94348.TBTitle.Table110.TRANGE.Trace.Range.Encoding) 3477 0 R (M9.9.95501.Heading5.14521.Normal.Mode) 3478 0 R (M9.9.96014.sectionxx.42.Comparator.Modes) 3479 0 R (M9.9.96120.TBTitle.Table114.CDCM.Encoding) 3480 0 R (M9.9.96218.tabletitle.Table.36.TRANGE.Trace.Range.Encoding) 3481 0 R (M9.9.97241.tabletitle.Table.11.Mode.Dependent.Restriction.Summary) 3482 0 R (M9.9.97341.sectionxxx.435.Trigger.Priorities) 3483 0 R (M9.9.97886.Heading4.1422.Exact.Address.Comparator.Match.Comparators.B.and.D) 3484 0 R (M9.9.99188.tabletitle.Table.33.COMRV.encoding) 3485 0 R (P.1) 3486 0 R (P.10) 3487 0 R (P.100) 3488 0 R (P.101) 3489 0 R (P.102) 3490 0 R (P.103) 3491 0 R (P.104) 3492 0 R (P.105) 3493 0 R (P.106) 3494 0 R (P.107) 3495 0 R (P.108) 3496 0 R (P.109) 3497 0 R (P.11) 3498 0 R (P.110) 3499 0 R (P.111) 3500 0 R (P.112) 3501 0 R (P.113) 3502 0 R (P.114) 3503 0 R (P.115) 3504 0 R (P.116) 3505 0 R (P.117) 3506 0 R (P.118) 3507 0 R (P.119) 3508 0 R (P.12) 3509 0 R (P.120) 3510 0 R (P.121) 3511 0 R (P.122) 3512 0 R (P.123) 3513 0 R (P.124) 3514 0 R (P.125) 3515 0 R (P.126) 3516 0 R (P.127) 3517 0 R (P.128) 3518 0 R (P.129) 3519 0 R (P.13) 3520 0 R (P.130) 3521 0 R (P.131) 3522 0 R (P.132) 3523 0 R (P.133) 3524 0 R (P.134) 3525 0 R (P.135) 3526 0 R (P.136) 3527 0 R (P.137) 3528 0 R (P.138) 3529 0 R (P.139) 3530 0 R (P.14) 3531 0 R (P.140) 3532 0 R] /Limits [(M9.9.76065.sectionxx.44.State.Sequence.Control) (P.140)] >> endobj 76 0 obj << /Names [(P.141) 3533 0 R (P.142) 3534 0 R (P.143) 3535 0 R (P.144) 3536 0 R (P.145) 3537 0 R (P.146) 3538 0 R (P.147) 3539 0 R (P.148) 3540 0 R (P.149) 3541 0 R (P.15) 3542 0 R (P.150) 3543 0 R (P.151) 3544 0 R (P.152) 3545 0 R (P.153) 3546 0 R (P.154) 3547 0 R (P.155) 3548 0 R (P.156) 3549 0 R (P.157) 3550 0 R (P.158) 3551 0 R (P.159) 3552 0 R (P.16) 3553 0 R (P.160) 3554 0 R (P.161) 3555 0 R (P.162) 3556 0 R (P.163) 3557 0 R (P.164) 3558 0 R (P.165) 3559 0 R (P.166) 3560 0 R (P.167) 3561 0 R (P.168) 3562 0 R (P.169) 3563 0 R (P.17) 3564 0 R (P.170) 3565 0 R (P.171) 3566 0 R (P.172) 3567 0 R (P.173) 3568 0 R (P.174) 3569 0 R (P.175) 3570 0 R (P.176) 3571 0 R (P.177) 3572 0 R (P.178) 3573 0 R (P.179) 3574 0 R (P.18) 3575 0 R (P.180) 3576 0 R (P.181) 3577 0 R (P.182) 3578 0 R (P.183) 3579 0 R (P.184) 3580 0 R (P.185) 3581 0 R (P.186) 3582 0 R (P.187) 3583 0 R (P.188) 3584 0 R (P.189) 3585 0 R (P.19) 3586 0 R (P.190) 3587 0 R (P.191) 3588 0 R (P.192) 3589 0 R (P.193) 3590 0 R (P.194) 3591 0 R (P.195) 3592 0 R (P.196) 3593 0 R (P.197) 3594 0 R (P.198) 3595 0 R (P.199) 3596 0 R] /Limits [(P.141) (P.199)] >> endobj 77 0 obj << /Names [(P.2) 3597 0 R (P.20) 3598 0 R (P.200) 3599 0 R (P.201) 3600 0 R (P.202) 3601 0 R (P.203) 3602 0 R (P.204) 3603 0 R (P.205) 3604 0 R (P.206) 3605 0 R (P.207) 3606 0 R (P.208) 3607 0 R (P.209) 3608 0 R (P.21) 3609 0 R (P.210) 3610 0 R (P.211) 3611 0 R (P.212) 3612 0 R (P.213) 3613 0 R (P.214) 3614 0 R (P.215) 3615 0 R (P.216) 3616 0 R (P.217) 3617 0 R (P.218) 3618 0 R (P.219) 3619 0 R (P.22) 3620 0 R (P.220) 3621 0 R (P.221) 3622 0 R (P.222) 3623 0 R (P.223) 3624 0 R (P.224) 3625 0 R (P.225) 3626 0 R (P.226) 3627 0 R (P.227) 3628 0 R (P.228) 3629 0 R (P.229) 3630 0 R (P.23) 3631 0 R (P.230) 3632 0 R (P.231) 3633 0 R (P.232) 3634 0 R (P.233) 3635 0 R (P.234) 3636 0 R (P.235) 3637 0 R (P.236) 3638 0 R (P.237) 3639 0 R (P.238) 3640 0 R (P.239) 3641 0 R (P.24) 3642 0 R (P.240) 3643 0 R (P.241) 3644 0 R (P.242) 3645 0 R (P.243) 3646 0 R (P.244) 3647 0 R (P.245) 3648 0 R (P.246) 3649 0 R (P.247) 3650 0 R (P.248) 3651 0 R (P.249) 3652 0 R (P.25) 3653 0 R (P.250) 3654 0 R (P.251) 3655 0 R (P.252) 3656 0 R (P.253) 3657 0 R (P.254) 3658 0 R (P.255) 3659 0 R (P.256) 3660 0 R] /Limits [(P.2) (P.256)] >> endobj 78 0 obj << /Names [(P.257) 3661 0 R (P.258) 3662 0 R (P.259) 3663 0 R (P.26) 3664 0 R (P.260) 3665 0 R (P.261) 3666 0 R (P.262) 3667 0 R (P.263) 3668 0 R (P.264) 3669 0 R (P.265) 3670 0 R (P.266) 3671 0 R (P.267) 3672 0 R (P.268) 3673 0 R (P.269) 3674 0 R (P.27) 3675 0 R (P.270) 3676 0 R (P.271) 3677 0 R (P.272) 3678 0 R (P.273) 3679 0 R (P.274) 3680 0 R (P.275) 3681 0 R (P.276) 3682 0 R (P.277) 3683 0 R (P.278) 3684 0 R (P.279) 3685 0 R (P.28) 3686 0 R (P.280) 3687 0 R (P.281) 3688 0 R (P.282) 3689 0 R (P.283) 3690 0 R (P.284) 3691 0 R (P.285) 3692 0 R (P.286) 3693 0 R (P.287) 3694 0 R (P.288) 3695 0 R (P.289) 3696 0 R (P.29) 3697 0 R (P.290) 3698 0 R (P.291) 3699 0 R (P.292) 3700 0 R (P.293) 3701 0 R (P.294) 3702 0 R (P.295) 3703 0 R (P.296) 3704 0 R (P.297) 3705 0 R (P.298) 3706 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